Bayer Image Noise Reduction Algorithm And Its Verilog Design And Verification

With the development of science and technology,digital imaging system has become an important part of daily life and production.In the fierce market competition environment,based on the actual needs of independent research and development,the image noise reduction algorithm for hardware implementation has become a research hotspot in the image field with the goal of low cost and high quality.Traditional noise reduction algorithms are based on a single noise,such as Gaussian noise,salt and pepper noise,and Poisson noise.However,in real life,noise is often complex and diverse.To this end,this dissertation performs an experimental study on the noise morphology and distribution of sensor based on real scene images.Through comparative experiments,the factors affecting sensor noise are identified,and the position of noise calibration in the image signal processing process is determined.Furthermore,this dissertation combines the noise calibration with the international organization for standardization in practical applications to fit the linear curve,which provides more direct and accurate noise information for subsequent noise reduction algorithms.The non-local mean algorithm occupies an important position in the spatial noise reduction algorithm because of its excellent edge preservation.On this basis,many other noise reduction algorithms have been developed.However,considering the noise reduction effect and the cost of hardware implementation,this dissertation presents an improved non-local mean algorithm for hardware implementation.The parameter selection of the original non-local mean algorithm is experimentally explored,then the effects of different key parameters selection on hardware resource consumption and algorithm performance are analyzed,and thus the results are optimized according to the experimental results.The original non-local mean algorithm has excellent edge preservation,but it has the issue of poor detail performance under low illumination.To address this issue,based on human visual system perception,image brightness weights are introduced to participate in image filtering for comparison experiments.The noise reduction effect of images in real scenes shows that this method can improve the detail performance of non-local mean algorithm in dark environment effectively.At the same time,since images in natural scenes often contain a large amount of high-frequency information,when smoothing with noise reduction algorithm,some high-frequency details will be removed to make the overall image blurry and greatly affect the visual perception.Therefore,in this dissertation,the noise overlay of the noise reduction results can effectively solve the ambiguity problem caused by the noise reduction algorithm by releasing part of the high frequency information without affecting the overall vision.The algorithmic production depends on the combination of hardware and software.Based on the development requirements of performance,power consumption,area and cost,this dissertation analyzes the hardware resource consumption of the proposed algorithm from the overall framework,and divides this algorithm into functional blocks on the logical circuit with the pipelining design structure.In the logic design,this dissertation analyzes the performance and cost differences of the main resource consumption modules in different ways.On the basis of satisfying the function development,a large number of logic devices are multiplexed to achieve the purpose of chip area compression.At the same time,low power technology is used to save energy.This dissertation relies on the universal verification methodology to set up a complete validation environment,and simulates and validates the designed logic circuit,which achieves the comparison of random test,directional test and automated results,verifies the functionality,completeness and practicability of the design.Through comparative analysis of Design Compiler,the logical design of this dissertation has the advantages of small area and low cost when the performance and power consumption can meet the requirements.Through coverage collection analysis,it can verified that the logical design does not contain code redundancy and meets the needs of functional development.Finally,the noise reduction results of hardware output are compared with those of other algorithms.The experimental results show that the improved algorithm has obvious advantages in clarity and detail performance,and the logic design with simulation validation and regression convergence can be integrated into image processing chip to achieve product.