VLSI Design And Verification Of Chrominance Denoising Module Based On Guided Filtering And Chrominance Reduction Mechanism

With the development of technologies such as digital communication,machine vision,and digital video multimedia,people have increasingly high requirements for image quality.It is not only necessary to eliminate brightness noise in images,but also increasingly important to eliminate chromaticity noise.In the fields of security monitoring,medical imaging,and video signal processing,the removal of chromatic noise is indispensable.Therefore,studying the chrominance denoising technology in image processing has very practical and extensive engineering meaning.Starting from practical applications,this dissertation studies algorithms that can remove basic chrominance noise efficiently in digital video image processing,and completes the hardware design and verification of a chrominance noise removal module based on guided filtering and chrominance reduction mechanisms.Firstly,the basic principles of chromaticity are introduced.Secondly,the causes and characteristics of basic chromaticity noise,such as color difference and purple edge issues,false colors,and color edges of overexposed images are introduced.After studying and comparing various digital image filtering methods,a chrominance denoising algorithm based on guided filtering and chrominance contraction mechanism suitable for hardware implementation is proposed.The algorithm mainly includes two denoising modules,namely,guided filtering and chrominance reduction.Guided filtering is based on the statistical information of luminance and chrominance channels calculated by a filtering window,uses luminance information as a reference,and considers the correlation between chrominance and luminance statistics for denoising;Chromaticity reduction performs eigenvalue shrinkage on the color matrix of the image filtering window to reduce color artifacts,preserves primary colors and suppresses secondary colors when reconstructing color images.Simultaneously,the noise analysis is introduced to improve image quality by adjusting corresponding parameters according to different types of noise.The processing result of the algorithm is analyzed by algorithm processing and parameter adjustment results.It can be shown that this algorithm can suppress purple edges,dark spots,and edge color errors effectively.In the implementation of the algorithm’s Very Large Scale Integration Circuit(VLSI)design,the commonly used low-power technology and synchronization technology in the design are firstly introduced,followed by a comprehensive consideration of chip power consumption,performance and area(PPA).Using pipeline design ideas,the architecture design and functional module division of the chroma denoising hardware system are carried out,mainly including statistical information calculation module,noise priority estimation module,guided filter module,and chromaticity shrinkage module.Then,under the premise of ensuring acceptable data transmission efficiency,the architecture is optimized in terms of chip area.The parallel computation of the two chroma channels has been changed to serial processing,which greatly saved area overhead.At the same time,the design optimizations of local circuit are introduced.After completing the hardware design and development,this dissertation builds a simulation verification platform based on Universal Verification Methodology(UVM)and System Verilog,and performs simulation verification on the design under test.Subsequently,test points are decomposed and test cases are written based on the functions and application scenarios of the chroma denoising system to ensure that the verified function points are tested.After analyzing the basic typical use cases through simulation waveform analysis,a large number of seed regressions are conducted on the test cases to collect code coverage to ensure code quality,while collecting functional coverage to ensure complete system functionality.Then,the logic synthesis of the design is performed under the S28 process library,and the comprehensive area report and timing report of the designed circuit are analyzed.Next,a real code stream test is conducted on the design using real images as input to verify the filtering effect of the designed algorithm.It can be shown that the designed hardware system meets the timing requirements,the clock frequency can reach 475MHz,and the total area of the optimized hardware system is 160405μm~2,the power consumption is 0.27m W,with a total of 38 pipeline stages.The image quality of the real color noise image has been improved significantly after algorithm processing and meets the expected requirements.