Research On Data Receiving And Storage Technology For High Order Amplitude Modulation System

With the continuous popularization and maturity of cloud computing,Internet of things technology,photoelectric information processing technology and artificial intelligence technology,data centers will face the explosive growth of traffic.In the field of optical communication,the demand for data transmission capacity is increasing.On the one hand,systems based on traditional non-return-to-zero(NRZ)signal transmission technology are subject to the severe requirements of transmission link time margin.On the other hand,high frequency signals will produce significant losses through channels.Therefore,it is difficult to meet the increasing data throughput requirements of emerging applications.X-level Pulse Amplitude Modulation(PAM-X)signals with multi-level series carry more information than NRZ signals in unit cycle,which can greatly alleviate the demand for channel bandwidth at the same rate.Therefore,it is widely used in the field of high-speed optical interconnection.The receiver transmission circuit and storage system of PAM8 signal are designed in this work.In terms of signal receiving,a 60 Gb/s PAM8 signal receiver system is designed based on 65 nm CMOS technology,which mainly includes comparator array,re-timer array and timing logic discriminant circuit.A rail-to-rail pre-amplification circuit is designed for the encoding level mode of PAM8 signal.Considering the influence of input transconductance on loop gain and signal distortion,the constant input transconductance of comparator is realized by adding a bias circuit.A high-speed retimer is designed in the analog domain to realize the synchronization of high-speed timing signals.The sequential logic discriminant circuit decodes the multi-channel sequential signal and restores it to three-channel NRZ signal.In terms of signal storage,the storage design of PAM8 signal is realized based on RRAM device,including the design of storage array and peripheral read-write circuit.The storage unit adopts the structure of 3T3 R,which stores three signal bits with different weights corresponding to the level states of PAM8 signal.In the writing operation,the corresponding decoding circuit is designed to complete the selection of each storage unit,and the two-terminal voltage of the device is precisely controlled to achieve the FORMING,RESET and SET operations of the memory device.In reading operation,a voltage sensitive amplifier with high precision and low power consumption is designed,and the accurate reading of stored data is realized by combining the corresponding data decoding circuit and multi-channel selection circuit.A high-speed PAM8 signal receiving and storage circuit is designed in this work.The simulation results show that the designed comparator circuit can generate stable decision output under the input voltage difference of 10 m V,and the transconductance does not change more than 8% within the input voltage range.Under different processing and temperature conditions,the eye image of output signal has no obvious jitter,and the eye image opening degree is above 0.92 UI.The delay time of the voltage sensitive amplifier does not exceed 40 ps at 0.3 V bit-line voltage difference.