Research On DMA Scheduling Model And Hardware Structure In Many-Core Cryptographic SoC

As the demand for high-speed cryptographic processing increases further,the integration of manycore cryptographic processors within a System On Chip(SoC)has become an important direction for high-performance cryptographic SoC design.By integrating a small number of general-purpose cores and several different types of dedicated task cores in the SoC via bus or Network-on-Chip(No C),the task cores can be used at different levels of granularity,allowing the system to have high performance while taking into account good flexibility and scalability.However,as the scale of task cores increases further,the large number of private stores increases the number of transfer requests in the system,which brings three problems affecting the performance of data transfer in the system: the scheduling problem of multiple data streams,the performance bottleneck problem of access memory conflict caused by a large number of requests,and the problem of data stream synchronization control overhead.Therefore,this topic focuses on the high-speed communication and transmission requirements in crowdsourced cryptographic SoCs.Based on the study of the data flow characteristics of crowdsourced cryptographic SoC architecture and cryptographic services,we focus on three aspects of DMA scheduling model,efficient DMA transmission mechanism,and intra-cluster data flow control to study the factors and solutions that limit the data transmission performance in crowdsourced cryptographic SoCs,and our main work is as follows:(1)A DMA allocation model between clusters of multi data streams in SoC is proposed to address the scheduling problem of multi data stream transmission in SoC.By analyzing the key factors affecting DMA transmission performance and combining the characteristics of multitasking data stream processing,a more accurate modeling of DMA scheduling problem is carried out.On this basis,a scheduling model analysis method based on task cluster allocation scheduling primitives was proposed,and the optimal inter cluster DMA allocation scheduling strategy was obtained through this analysis method.Through experiments,it can be seen that the DMA scheduling model in this paper can better fit the actual situation.When using the same DMA controller,the obtained scheduling strategy improves the overall performance of multi algorithm and multi task by 22.55%.(2)An improved DMA transmission mechanism and hardware structure are proposed to address the performance bottleneck caused by access conflicts caused by a large number of requests.Analyze the conflict generation mechanism and conflict transmission mechanism of multi channel memory access in the SoC,propose an improved Outstanding transmission mechanism based on AXI bus,and conduct hardware design based on this.The design includes multiple full duplex channels to support the Pesudo Fly by transmission mode.The DMA controller supports multiple configuration information inputs and dynamically adjusts the request lifecycle,switching transmission in a timely manner to avoid conflicts.(3)A micro instruction data flow controller structure based on index table is proposed to address the scheduling problem of data flow control within the SoC cluster of multi core cryptography.By designing a dedicated low resource utilization data flow control circuit and maintaining the task packet index of the data flow entering the task cluster,flow control and sequential processing in the scenario of multiple data flow random intersections are achieved,while solving the problem of duplicate configuration in the output process of processed data.The data flow controller,in conjunction with the DMA controller on the bus,achieves two-level scheduling of data from the storage area to the task core in the multi core cryptographic SoC.