Research And FPGA Implementation Of 1000BASE-T Physical Layer Equalization Technology

The 1000BASE-T transmission scheme based on the 802.3ab standard not only achieves a high transmission rate of 1Gbps,but also provides full compatibility with resources such as existing applications and network management.1000BASE-T Gigabit Etherent em-ploys multi-level joint coding modulation and targeted digital processing technology to achieve full-duplex high-speed transmission over unshielded twisted pair of Category 5e at 125MHz.However,the transmitted symbols are interfered by various types of channel interference different from 100BASE-TX,resulting in severe distortion of the received symbols.And a high-complexity trellis decoding algorithm is employed at the receiver to achieve the target bit error rate of less than 10^-10,which puts forward strict requirements on the performance of the baseband signal processing module at the receiver.In this context,the thesis conducts an in-depth study on the 1000BASE-T transceiver architecture.As to symbols that are severely distorted after passing through the transmis-sion channel,the performance of different joint equalization decoding schemes is analyzed in detail by constructing a simulation model of 1000BASE-T communication links.The main research contents are as follows:（1）Aiming at the situation that the received symbols of 1000BASE-T are seriously distorted and the symbols after the linear equalizer still exist postcursor intersymbol in-terference,a joint DDLMS-DDCM dual-mode blind equalization algorithm applied to the decision feedback equalizer is proposed.The algorithm combines the respective advan-tages of DDLMS and CMA algorithms,and controls the ratio of the two blind equalization algorithms through weighting functions to speed up convergence and reduce residual er-rors.After adjusting the relevant parameters and analyzing the bit error rate,it can be seen that the algorithm can achieve fast convergence without damaging the performance of the equalizer.（2）Aiming at the slow-changing channel characteristics of 1000BASE-T and the re-striction that the transmitted symbols are priori unknown for the receiver,a decision feed-back pre-filter+parallel decision feedback decoding structure based on real-time channel estimation is designed.Decision feedback pre-filtering is used to truncate the tail of back-ward channel coefficients,and the estimated value of intersymbol interference is applied to the branch metric unit of the parallel decision feedback decoding trellis by accurately estimation of the postcursor channel coefficient.The symbol error rate index is used to compare the performance of several equalized decoding structures.According to the sim-ulation results,it can be seen that the decision feedback pre-filtering+parallel decision feedback decoding structure further reduces the complexity of trellis decoding without significantly affecting the bit error rate,and meets the requirements of 1000BASE-T trans-mission.（3）A communication link simulation model based on the MATLAB platform is built,and the complete simulation process of coding and modulation at the transmitter,channel modeling,and equalization decoding at the receiver is realized.On this basis,the imple-mentation logic of the physical coding sublayer of the sending end is studied in depth,and the digital domain of transmitter is realized based on the FPGA hardware development platform.