Research On Reliability And Mechanism Of P-GaN Gate HEMTs Under Off-state Stress

With its advantage of simple process,good consistency and low cost,p-GaN gate HEMTs（GaN High Electron Mobility Transistor）have become the mainstream enhanced implementation scheme in the industry.And gradually used in fast charge,data center,laser radar and other high-frequency,high power density fields.Despite these superior material properties and the emerging commercialization trend,p-GaN gate HEMTs have reliability issues such as current collapse and threshold voltage instability,which have become bottlenecks and obstacles to their sustainable development.In order to further promote the application and development of GaN devices,this thesis discusses the reliability problems of p-GaN gate HEMTs devices in practical applications and reveals the underlying physical mechanism leading to the degradation of devices.The main research of this thesis is summarized as follows:（1）The electrical degradation mechanism of p-GaN gate HEMTs under negative gate voltage off-state bias stress was revealed.In this thesis,the negative gate voltage steady-state stress test was carried out on p-GaN gate HEMTs to research the influence of long-term negative gate voltage off-state stress on device reliability.Negative gate voltage off-state stress can cause significant threshold voltage positive shift and degradation of saturation drain current.Significant V_TH shift of+0.68V and saturation current reduction up to 66.7%are observed under the stress condition of V_GS=-4V@V_DS=80V.And with the increasing negative gate bias voltage and drain bias voltage,and lower working environment temperature,the more significant degradation was found.By combining with the simulation of Sentaurus TCAD,it is found that the positive shift of threshold voltage is due to the negative gate voltage promoting the hole emission in p-GaN layer and the electron trapping in gate-stack,while enhancing the trapping process of channel electron overflow by traps in gate-stack.However,the carrier transport in the gate-stack region and the channel electrons filled the Si N/Al GaN interface traps in the gate to drain access region lead to the decrease of saturation drain current.The high temperature can suppress the positive shift of threshold voltage by suppress the hole emission in p-GaN layer and promoting the electron de-trapping in in the gate stack.（2）The electrical degradation mechanism of p-GaN gate HEMTs under self-heating effect is comprehensively investigated.The DCI stress technique is proposed to investigate the self-heating-induced instability of p-GaN gate HEMTs in this thesis.Significant V_TH shift of+0.83 V and drain current reduction up to 18%,corresponding to the chip temperature of 150°C,versus V_TH shift of+0.25 V and drain current reduction up to 11%corresponding to the chip temperature of 70°C are observed under different DCI stress.Meanwhile,device characteristics and recovery dynamics after degradation and electrothermal TCAD device simulation are studied to reveal the underlying mechanisms.The self-heating-enhanced electron trapping in the p-GaN gate-stack responsible for V_TH instability,the self-heating-enhanced electron trapping in the p-GaN gate region,and the access region beneath the first source field plate at the Si N/Al GaN interface account for the drain current degradation.