Study On ESD Characteristics Of AlGaN/GaN Heterojunction Devices

The third generation semiconductor material GaN has the ability to withstand high temperature and voltage.AlGaN/GaN heterojunction structure is often used to make SBD and HEMT.The devices have the advantages of high electron saturation velocity and high electron density,which makes the devices have a far-reaching application prospect in the field of high-frequency,high-voltage,and high-power integrated circuits.However,the research on AlGaN/GaN heterojunction structures in the ESD field is still at a preliminary stage.Improving the ESD protection ability of devices is the guarantee for achieving their large-scale industrial applications.In this thesis,with the aid of TCAD Sentaurus,research on SBD and HEMT with AlGaN/GaN heterojunction structures has been carried out in the ESD field.The following are the main work and achievements of this article:(1)For AlGaN/GaN SBD,the effects of Al composition in barrier layer,the thickness of barrier layer and the space between electrodes on the ESD characteristics were studied.It is found that increasing the composition of Al in barrier layer,increasing the thickness of the barrier layer and reducing the space between electrodes can reduce on-resistance of the device and improve the current discharge ability of the device in ESD protection.(2)For AlGaN/GaN HEMT,the influence of ESD on the output and transfer characteristics and its causes were studied.It is found that when ESD occurs,a large electric field will generate near the gate of the device,causing hot electrons to be injected into the trap at the interface which is between the cap layer and the passivation layer.So an electron depletion region form at the two-dimensional electron gas region,impeding the flow of current from the drain to the gate and source.(3)In view of the phenomenon of hot electrons injected into the traps at the interface between the cap layer and the passivation layer of AlGaN/GaN HEMT after an ESD event,specific schemes to improve its ESD resistance ability are discussed from the perspectives of interface trap parameters and adding field plates.It is found that reducing the concentration of interface traps,eliminating deep level interface traps with energy levels greater than 0.68 e V from the conduction band,and using a field plate with a passivation layer thickness less than 150 nm can effectively reduce the impact of ESD on the device.