Design And Implementation Of Hardware For Homomorphic Encryption Computations Acceleration Based On FPGA

In cloud computing scenarios,data owners want to minimize the risk of leakage of sensitive data during computing,but traditional encryption algorithms lack support for computing,so that the executor can only process plaintext data.To cope with this dilemma,a homomorphic encryption algorithm that supports ciphertext computation is proposed.However,compared with plaintext calculations,current homomorphic encryption calculations face the challenge of computational efficiency.This constitutes a major obstacle to the further deployment of such algorithms.The problem is that in the face of high-cost homomorphic encryption calculations,mainstream computing architectures,such as CPUs or GPUs,cannot well adapt to the basic arithmetic and data flow characteristics of homomorphic encryption calculations,and provide targeted hardware arithmetic units and parallel computing and memory access mechanism.In order to solve the above problems,this paper studied the algorithm of homomorphic encryption and its hardware implementation.Combined with the status quo of homomorphic encryption algorithm which is still in the stage of continuous evolution,the requirements of computing efficiency,algorithm adaptability and deployment cost are comprehensively considered,and the advantages of FPGA over hardware platforms such as CPU,GPU and ASIC are clarified.On this basis,a FPGA-based homomorphic encryption computing hardware design is proposed.The main work is as follows:(1)A theoretical analysis of homomorphic encryption was carried out to prepare for hardware design.Firstly,the principle of the basic arithmetic,that is,modular arithmetic is analyzed.Then,the bottleneck of homomorphic encryption calculation was located at ciphertext multiplication,and the principle and complexity of its special arithmetic with polynomials as operands was analyzed,and then the theoretical method of Number Theoretic Transform(NTT)combining negacyclic convolution and fast Fourier transform was introduced and analyzed for the complexity optimization.(2)For the calculation of modular arithmetic,the modular addition and subtraction units based on conditional subtraction and addition and the modular multiplication unit based on Barrett modular reduction are designed.At the same time,the resource consumption was optimized through logic reuse,and the optimization analysis of the hardware word length ensures the efficient utilization of the hardware multiplier.On this basis,the modular arithmetic butterfly unit was designed,and the data path of the butterfly unit is optimized by using the feature that the twiddle factor can be pre-calculated.(3)For the optimal calculation of polynomial multiplication,NTT and INTT modules was designed based on the aforementioned modular arithmetic unit.In the design,the cross-stage invariance of the complex data flow of NTT was excavated,and then a parallel computing data mapping mechanism and the corresponding fully pipelined hardware design were proposed,eliminating unfavorable factors such as data risk,pipeline bubble and space domain data rearrangement completely,ensuring correct functions,efficient calculations,and saving resources at the same time.Finally,the simulation and synthesis of the RTL design coded in Verilog was carried out in the Vivado development environment,and compared with previous work,the design of the NTT/INTT module achieved 80%～93.9% fabric resource saving,showing the correctness of the hardware design in this paper and the effectiveness of the proposed parallel computing data mapping mechanism in saving hardware resources.