Research On Gate All Around Nano Wires Field Effect Transistors And Their Applications In Synaptic Device

In recent years,the rapid development of artificial intelligence and big data technology has put forward higher requirements for chip computing power.With the continuous shrinkage of device size,the development of traditional FETs has approached its physical limit,and the development of new principles and new structures in the post-Moore era FETs has become an urgent need at present.On the other hand,the computing power of traditional computers based on von Neumann’s architecture is also facing great challenges,and brain-like neuromorphic computing has become a research hotspot.III-V nanowires have unique one-dimensional structural characteristics and novel physical properties,and show great application potential in novel FETs and synaptic devices.In this paper,the main achievements and innovations of this paper are as follows:Firstly,A gate all around GaAs nanowire field effect transistors based on high K dielectric was designed.By using HfO2 instead of SiO2 as the gate oxide,the current Ion/Ioff of the device is increased from 105 to 107,the threshold voltage was increased by 23 percent,and the subthreshold slope was reduced from 85 mV/dec to 62 mV/dec.The influence of device parameters on its performance was also studied,and it was found that the current Ion/Ioff of the device decreased as the gate length decreased;As the nanowire radius and gate oxide thickness decrease,the current Ion/Ioff of the device increases.At the gate length of 10 nm,nanowire radius of 3 nm,and oxide thickness of 2 nm,Devices Based on high K dielectric has a threshold voltage of 0.33 V and a subthreshold slope of 62 mV/dec.Secondly,A synaptic device based on the gate all around InAs nanowire field effect transistors was designed.The deposited oxide layer(In2O3)on the InAs nanowire surface serves as a charge trapping layer for information storage.At low gate voltages,synaptic behavior such as short-term depression(STD)and long-term depression(LTD)is simulated.By increasing the amplitude and quantity of gate voltage pulses,the transition from STD to LTD is realized.The device has a large memory window of over 1 V and a minimal energy consumption of 12.5 pJ per synaptic behavior.