| With the rapid developing of wireless communication technology,human’s demands for miniaturized,portable and high-performance wireless communication devices are getting higher and higher.The RF front-end chip is a key component of wireless communication equipment.Based on CMOS technology,this thesis designed a wide-band RF receiving front-end chip.The specific work of this thesis is as follows:1.The various topological structures of Low Noise Amplifiers(LNA)were compared,and the detailed theoretical derivation of the performance indicators was carried out.The noise cancellation structure in the wide-band LNA type was selected,analyzed the principle of noise cancellation,and a wide-band LNA with adjustable gain was finally improved.The working frequency range of the designed LNA is 300MHz～900MHz,when the load resistance is 50W,the voltage gain can reach to 19 dB,the gain adjustment range is 6dB,the noise figure is less than 2.7dB under different working conditions,the working voltage is1.8V,and the power consumption is about 5.5m W.2.The working principle of the Mixer was theoretically deduced,the structure and characteristics of the passive Mixer and the active Mixer were compared.The performance indexes of the Mixer were analyzed.Finally,a current source assisted active single balanced Mixer was improved and designed.In the working frequency range of 300 MHz ～ 900 MHz,the conversion gain of analyzed Mixer is 30 dB,the noise figure is less than 5dB,the output1 dB compression point is about 0dbm.The working voltage is 1.8V,and the power consumption is about 1.9m W.3.In the Phase-Locked Loop(PLL)circuit that generates the local oscillator signal of the Mixer,a reference frequency source is required.Therefore,in addition to the above work,this thesis deduced the principle of the crystal oscillator in detail,and designed a crystal oscillator with the Santos structure.The oscillation frequency is 10 MHz,driven by a three-stage inverter to output a stable 10 MHz square wave signal.And designed a Low Dropout Regulator(LDO)circuit,when the input power supply voltage range is 2.5V～3.3V,it can provide 1.8V stable power supply for the above circuit modules.4.The layout of the designed circuit modules was drawn,and the layout of each module was cascaded,achieved complete chip layout.The post simulation results show that the RF front-end chip designed in this thesis,in the working range of 300 MHz ～ 900 MHz,the system conversion voltage gain is between 40 dB ～ 50 dB,the noise figure is less than 3.7dB,and the output 1dB compression point can reach to 0.22 dBm.The chip area is 824um×788um. |
