Design And Optimization Of Three Dimensional Stacked Packaging Structure For Memory Chips

With the continuous development of electronic information technology,higher requirements are put forward for the ability of information storage,which promotes the chip packaging technology to develop towards miniaturization and high integration.The appearance of three-dimensional packaging technology greatly increases the utilization ratio of storage capacity and packaging area,which is widely used in memory packaging.However,because of the material characteristics of plastics,there are reliability problems such as warpage delamination and wire sweep in the packaging process,so the failure risk caused by high junction temperature should be considered in practical application.Therefore,rational design of three-dimensional packaging structure optimization is an effective method to improve device reliability from the perspective of the production process.The paper regards the chip stack interlaced packaging structure of memory chips as the research object.Considering the viscoelasticity of the molding compound,the paper intends to explore the influence trend of different factors on the performance of the packaging from packaging reliability and plastic-packaging technical feasibility which builds the fundamentals to make an optimization analysis,coming up with the optimization scheme.The specific research contents of this paper include:(1)The mechanical properties research and experiment of epoxy molding compound are conducted according to the generalized Maxwell model,which works as the basis of full-text simulation analysis.In the dynamic mechanic’s experiment,the storage modulus,glass transition temperature T_g and other basic material parameters are obtained by DMA.The storage modulus main curve is constructed and processed by time-temperature equivalency theory,then,the shear relaxation constant and bulk relaxation constant are obtained.In the thermo-mechanical analysis experiment,TMA is used to obtain the correlation curve of sample size change and temperature,the secondary detection of glass transition temperature T_g is completed,and the corresponding thermal expansion coefficient is gained.(2)In terms of package reliability,the influence of the change from package structure parameters on packaging warpage,thermal stress,and chip junction temperature are mainly considered through simulation analysis.The simulation results show that affected by the viscoelastic properties of the molding compound,stress relaxation occurs in the high-temperature stage,and the thickness of the molding compound is the main factor to affect the warpage.As for thermal performance,influenced by multiple internal heat sources,a certain thermal coupling phenomenon happens between chips,and the thickness of the adhesive is the major factor to impact the junction temperature.Based on the above conclusions,the influence of packaging warpage should be given priority to be considered.By adopting a weighted score into the range analysis,the order of the influence of structural parameters on packaging performance is illustrated as follows:adhesive thickness,molding compound’s height,and chip thickness.The maximum warpage of the optimized structure is 18.21μm,and the maximum junction temperature is 54.43℃.(3)Concerning plastic-packaging technical feasibility,the research analyzes the stacked packaging molding technique of memory chips,to explore how gate scheme setting and various technological parameters affect the transfer molding process.When adopting the single gate scheme,the wire sweep and melt conversion rate are compared and analyzed as measured indicators by the single-factor analysis method.The results demonstrate that the effect of melt flow is the tradeoff between flow rate and viscosity change,and the test results all show a strong dependence on molding temperature.The variation trend of the above two test results is comprehensively evaluated,meanwhile,the primary and secondary order of factors that affect the molding process is obtained as follows:molding temperature,melt temperature,and filling time.In conclusion,the article preliminarily elaborates on how component material and changes in plastic-packaging technological parameters influence the stacked packaging performance of memory chips and aims at providing guidance for the practical production stage to some extent.