Research On Key Technologies Of Elliptic Curve-oriented High Performance Computing Architecture

With the advent of the digital information age,how to ensure information security has attracted attention from all walks of life.As one of the public key cryptosystems,elliptic curve cryptography is highly respected for its short key,high security level,and fast processing speed.After continuous improvement by cryptographers,elliptic curve cryptography has gradually become the development direction of the new generation of cryptography technology and has a good development prospect.The computer’s needs for the elliptic curve cryptosystem’s performance go up as network bandwidth requirements grow as well.Scalar multiplication and finite field operations,which are the fundamental operations of elliptic curve encryption,have significant levels of complexity,making it more challenging to enhance system performance.Therefore,this paper conducts an in-depth analysis of elliptic curve cryptography,studies the key technologies of the high-performance computing architecture of elliptic curves from the two levels of elliptic curve scalar multiplication and finite field operations,and gives specific solutions based on the modular design idea.The main research content of the paper is as follows:(1)The operation scheduling of the Karatsuba-Ofman algorithm is optimized,the utilization rate of the multiplier and the adder is improved,and the multiplication operation only needs 3 clock cycles.(2)The fast modulus reduction algorithm of secp256k1 curve is designed by using the bit reorganization method,and the fast modulus reduction algorithm of secp256r1 and SCA-256(SM2 standard recommended curve)are designed respectively by using this method.Then,according to the fast modular reduction algorithm,a hardware architecture that supports the fast modular reduction calculation of the three curves secp256r1,secp256k1 and SCA-256 is proposed.(3)The multiplication operation and modular inversion operation are integrated into one unit design,and a resource-sharing operation unit hardware architecture is proposed.The operation unit can realize two functions of multiplication operation and modular inverse operation,share internal registers and adders,and improve the utilization rate of hardware resources.(4)According to the characteristics of the finite field computing hardware architecture,the modulo operation scheduling of point addition and point double is optimized.A modulo calculation operation scheduling method combining doubling and adding operations is proposed,which further improves the calculation speed of dot calculations.Finally,three curve scalar multiplications are integrated into one unit for design,and a high-performance scalar multiplier hardware architecture is proposed.This article performs logic synthesis on the architecture using the 55 nm and 130 nm CMOS processes.According to the synthesis results for 55 nm,the clock frequency is500 MHZ,the area is 275 k equivalent gates,the throughput is 48309 times per second,and the AT can be up to 5.7.According to the synthesis results for 130 nm,the clock frequency can be up to 243 MHZ,the area is 314 k equivalent gates,the throughput is23529 times per second,and the AT can be up to 13.345.In addition,the Virtex-7 is used for design verification on the FPGA platform.The comprehensive results of Virtex-7 showed that the clock frequency is 37 MHz,the area is 47.4K LUTs,the throughput is 3584 times per second,and the AT can be up to 13.2.