| With the rapid development of information networks,all kinds of data are influencing people’s lives all the time.With the wide spread of information,the requirements for information confidentiality and transmission security are getting higher and higher.Therefore,research in the fields of information security and cryptography has gradually become the key guarantee of national security.China is a country that emphasizes the independence and controllability of cryptographic technology,and the SM9 algorithm is an independently researched identification cryptographic standard released by China in 2016.Among them,bilinear pairing is the core operation in SM9,and the optimization of its efficiency becomes the key to improving the performance of the SM9 algorithm.With the core goal of improving the operation efficiency of bilinear pairs,this paper studies the calculation process of Optimal-ate bilinear pairs,improves the modular multiplication operation,and designs the overall algorithm accordingly.The core of the SM9 algorithm is bilinear pairing.It is an algorithm based on the extended field structure,in which the prime field and the quadratic extended field are the basic fields of operation.Since modular multiplication accounts for about70%of the total operation,optimization of the modular multiplication algorithm can greatly improve the computational efficiency of bilinear pairs.This paper mainly studies in the following aspects.(1)The Karatsuba multiplication formula suitable for input 256 bits and multiplier 64 bits is derived for large integer multiplication.On this basis,a parallel Montgomery modular multiplication is proposed to accelerate the modular multiplication in prime fields.(2)This paper proposes aKA-Fp~2 modular multiplication algorithm which is applicable to both IBC system and SM9 algorithm for quadratic extended field.This algorithm can greatly reduce redundant calculations in modular multiplication of twice expanded domains,including multiplication times and modular reduction times required for calculation.At the same time,this paper also makes a detailed parallel timing arrangement for the above two modular multiplication algorithms to maximize their resource utilization.(3)This paper further proposes the hardware architecture of the Montgomery modular multiplication algorithm and theKA-Fp~2 modular multiplication algorithm,which can be used for parallel computing,and implements the bilinear pair architecture based on the above modules.The design in this paper uses a 66-bit multiplier.Under the standard process of TSMC 55nm,the highest clock frequency of the parallel Montgomery mode multiplication architecture in the prime field can reach 2.0 GHz,and the area is 90K equivalent gates.It takes 8 ns to complete a modular multiplication calculation.Under the same process library,the KA-Fp~2 modular multiplication architecture designed in this paper can complete the modulo multiplication calculation of the first and second domain expansion at 9.5 ns at the clock frequency of 2.0 GHz,with an area of 209K equivalent gates.Compared with the existing literature,the modular multiplication structure designed in this paper is superior to similar designs in terms of circuit area,time required for modular multiplication calculation,and area-time product.The corresponding bilinear pair operation unit has an operating frequency of 500 MHz and an area of 824K equivalent gates.Through comparison,the improved bilinear pair computing unit has obvious performance improvement compared with other similar designs. |
