Link-16 Data Chain Full Airspace Enhancement Waveform FPGA Implementation Study

Link-16 is a decentralized data chain that is used by various types of equipment.In the aircraft application scenario,due to the special application platform,when the aircraft is maneuvering in the air,the communication between terminals will be interrupted due to the blockage of the direct signal path by the fuselage and wings.Based on the above scenario,this thesis designs a full airspace enhancement waveform based on space-time packet codes;the introduction of space-time packet codes leads to an increase in the sensitivity of the transmission waveform to timing errors.To ensure the functionality of the system,the classical frequency hopping synchronization method is modified in this thesis.The main contents of this thesis are as follows:First,a two-transmit-two-receive communication design scheme based on space-time packet codes is proposed for solving the effect of airframe occlusion on communication.Firstly,four communication scenarios are constructed based on the typical characteristics of the aero channel.Since the combination of Alamouti coding and continuous phase modulation will result in phase discontinuity,the L2-Orthogonal ST-Code is used for the design instead.This method can make the introduced spectrum expansion smaller while ensuring the signal phase continuity.The simulation results show that the L2-Orthogonal ST-Code improve the SNR performance by 2-7dB compared with classical coding methods when the BER reaches 10^-4.Second,since the system using space-time packet codes is more sensitive to timing deviation,a new frequency hopping synchronization method is designed in this thesis.In the coarse synchronization,any two frequency hopping frequencies are combined into one judgment statistic,and the four judgment statistics are subsequently judged by the P/Q method;in the precise synchronization algorithm,the interpolation method is used to improve the synchronization accuracy in consideration of the implementation complexity and resource consumption.Simulation shows that:under the requirement of timing accuracy[-T/10,T/10],the improved synchronization method has a synchronization success rate of more than 99%at a signal-to-noise ratio of about-5dB in a Gaussian channel and more than 99%at about-4dB in a fading channel,and the performance is improved by about 1～3dB compared to the classical method in scenarios with different kinds of interference to meet the requirements of the transmission waveform on timing deviationThird,the overall system is implemented on the XCVU11P FPGA hardware platform,and the system performance is tested on the platform.Firstly,the FPGA implementation method and simulation results of the key modules of the link are given.Timing optimization methods are given for the high-speed clock domain part of the system.Finally,the chip resource consumption and the test performance are shown to verify the system performance.The test on the platform shows that compared to the floating-point simulation,the system performance under ideal synchronization is backed off by 0.4dB,and the system performance tested on the platform with synchronization is backed off by1dB,which meets the application requirements.