Research And Implementation Of Timing Synchronization In Segmented Adjustable Communication System

Segmented adjustable dedicated communication technology is one of the important research areas in both military and civilian communication fields.The technical solution of segmented adjustable dedicated communication systems should be flexibly adjusted based on the actual communication requirements in different time periods,with the ability to transmit data at different bit rates in segments.Timing synchronization,as an important component of segmented adjustable communication receiver systems,ensures that the receiver system can accurately receive and demodulate digital signals.In low-bit-rate transmission systems,timing synchronization design focuses on the reliability of data transmission.In high-bit-rate transmission systems,timing synchronization design needs to meet the requirements of transmitting highspeed data and focuses on the performance of error correction and handling under certain timing error conditions.Based on the analysis of the basic theory of timing synchronization and the requirements of segmented adjustable communication systems for segmenting data transmission,this thesis completes the design of a feedback-type timing synchronization framework.Based on the analysis of timing synchronization algorithms,the thesis designs a timing error estimation algorithm for segmented adjustable communication systems.Under low-bit-rate transmission conditions,the use of a serial structure for the classic Gardner timing loop with non-zero intermediate sampling and interpolation base point adjustments can cause timing jitter.Reducing timing jitter can lead to an increase in synchronization establishment time.To address these issues,the thesis proposes corresponding optimization scheme designs.Under high-bit-rate transmission conditions,the thesis parallelizes the serial structure-based timing synchronization scheme based on the Gardner algorithm.Based on the high complexity of multi-path interpolation,a parallel scheme is designed for joint frequency domain matching filtering and timing error detection based on the O&M algorithm under the APRX architecture.The thesis conducts MATLAB functional simulation and simulation verification.By setting different timing and frequency offsets,the timing synchronization schemes for lowbit-rate and high-bit-rate transmission systems are verified from multiple perspectives.The simulation results demonstrate the feasibility and effectiveness of the proposed design.The thesis implements the overall scheme in hardware using Verilog hardware description language and conducts testing and verification.Based on the different requirements of timing synchronization schemes for data transmission rate limitations in low-bitrate and high-bit-rate transmission systems,hardware platforms for low-bit-rate and highbit-rate transmission conditions are built using FPGA.Under restricted input conditions,the results of board-level testing experiments demonstrate the feasibility and effectiveness of the proposed design,achieving the research objectives.