Research And Implementation Of Carrier Recovery Technology In Segmented Adjustable Communication System

The segmented adaptive communication system is a specialized communication system that transmits information data with different bit rates during different communication periods.This system features dynamic adjustment of the transmission bit rate: it employs a low bit rate transmission scheme during periods suitable for low bit rate communication,and a high bit rate transmission scheme during periods suitable for high bit rate communication.The segmented adaptive communication system exhibits high communication efficiency and reliability,making it one of the current research focuses in the field of communication,particularly in military communication.Due to limitations imposed by key electronic devices such as FPGA in terms of their maximum operating frequency,high bit rate digital communication systems require the use of digital signal parallel processing techniques,which differ from the digital signal serial processing techniques employed by low bit rate digital communication systems.This thesis focuses on the carrier recovery technology of the segmented adaptive communication system,with the objective of achieving high-performance carrier recovery under both high and low bit rate transmission conditions.Extensive research work has been conducted on carrier recovery technology under high and low bit rate digital transmission conditions.Based on an analysis of the research dynamics of carrier recovery technology both domestically and internationally,this thesis conducts an analysis of the characteristics of the demodulation system architecture,determining the digital zero intermediate frequency(IF)demodulation architecture as the processing architecture for high and low bit rate carrier recovery.To address the issue of small frequency offset capture range in traditional phaselocked loop(PLL)structures,the thesis designs a carrier recovery algorithm combining forward open-loop and closed-loop PLL.This algorithm exhibits high accuracy phase locking under large frequency offset conditions.MATLAB simulation tools are employed to verify the designed carrier recovery algorithm.The simulation results demonstrate that the algorithm achieves a frequency offset capture range of up to 0.09 times the symbol rate,with remaining frequency offset residual in the order of 1E-9.These results validate the feasibility and effectiveness of the carrier recovery scheme proposed in this thesis.To overcome the slow convergence speed issue in traditional parallel processing architectures,this thesis designs a parameter-passing-based parallel processing architecture under the constraint of restricted input conditions.This architecture exhibits fast convergence speed under high-performance constraints.MATLAB simulation tools are used to verify the parallel carrier recovery algorithm.The simulation results indicate a convergence speed of fewer than 300 symbol points for the parallel algorithm,while achieving a frequency offset capture range of up to 0.014 times the symbol rate.These results validate the feasibility and effectiveness of the parallel carrier recovery scheme proposed in this thesis.This thesis develops segmented adaptive QAM modulation communication modules for 192 Mbps and 1.44 Gbps.It completes the hardware language design of the segmented adaptive carrier recovery algorithm and establishes an experimental verification platform to conduct corresponding experimental validation.The experimental results demonstrate the feasibility and effectiveness of the segmented adaptive carrier recovery scheme proposed in this thesis.