Design Of Analog Front End Circuit For ECG Signal Acquisition With High Common Mode Rejection Ratio

With the development of economy and society,peoples attention to their own health has gradually increased,which has also led to the flourishing development of wearable biomedical sensors.Wearable biomedical sensors enable real-time monitoring of human health and timely warning of possible abnormalities in the body,thereby reducing the prevalence,severity and mortality of users.A bioelectric signal acquisition and sensing system with excellent performance needs an analog front-end circuit with low power consumption,low size,low noise and high interference suppression capability.Bioelectric signal has the characteristics of low frequency and low amplitude,and is very vulnerable to external environmental interference and the noise of its own circuit.For two-electrode ECG signal acquisition system,the peak value of common mode interference signal coupled to human body by surrounding power lines can be as high as tens of volts,leading to the saturation of the front-end circuit.There is a large impedance mismatch between the dry electrode models,which will affect the common mode rejection ratio（CMRR）of the front-end circuit system,and will introduce the error of common mode slip mode.The electrodes react with human skin by introducing a larger DC electrode offset（DEO）voltage.In addition,the presence of an impedance voltage component in the signal pathway can cause signal attenuation.Finally,the noise in the front-end circuit will affect the accuracy of signal collection.To solve the above problems,this thesis presents a front-end circuit for two-electrode ECG acquisition,which is mainly composed of common-mode interference suppression module and signal amplification module.The signal amplification module is composed of instrument amplifier module and programmable gain amplifier（PGA）module combined with input impedance lifting technology.In this design,a common mode interference suppression module circuit is proposed to suppress the common mode interference signal.The integrated common mode replication technology can greatly increase the common mode input impedance to weaken the influence of electrode mismatch on the common mode rejection ratio.An adaptive input impedance lifting loop is presented to reduce the influence of input capacitance and input parasitic capacitance on the input differential mode impedance of the signal amplifier module.A capacitive coupled instrumentation amplifier is used to reduce the system mismatch caused by poor resistance matching compared with capacitance,and to achieve the performance index of low noise and low power consumption.Finally,three-pass gain（12/18/24 d B）adjustable PGA modules are used to meet different application scenarios.Based on 180nm BCD process,common mode interference signal with peak value up to 30 V_PP is suppressed at1.8 V power supply voltage.The total circuit transient output ENOB is 11.9 bit,SNR is73.76 d B and SFDR is 74.91 d B.For the signal amplifier module,the total current consumption to achieve is 3.41μA;With 100%electrode mismatch（1M||10n F）,the CMRR was 119.312 d B and the power rejection ratio was 119.508.At 50 Hz,the common mode input impedance is 272.54 GΩand the differential mode input impedance is 5.12GΩ.Equivalent input integral noise is 2.43μV in the frequency range 0.5-150 Hz.