Research And Circuit Design Of RF PA Efficiency Improvement Method For New Generation Wlan

In the past 30 years,the continuous popularization of intelligent equipment has greatly changed the way people communicate and led to higher requirements for network transmission rate,forcing the rapid development of wireless communication technologies.WLAN technology complies with the requirements of the generations and technical standards are constantly updated.The new generation WLAN technology not only provides greater bandwidth,but also provides higher-order modulation modes.The data throughput is up to 9.6 Gbit/s,and the delay is as low as 20 ms.However,a high PAPR and high power signal makes the design of a linear power amplifier more difficult,and it is easy to make the amplifier work in the saturated region,resulting in serious nonlinear distortion.In this regard,only the power back-off technology and other linearization technology can be used to alleviate this situation,which leads to the low peak efficiency of the power amplifier.The peak efficiency of the high linear power amplifier without the efficiency improvement technology will be about 27%.Therefore,it is of great significance to study and design a high-efficiency linear power amplifier applied to the new generation WLAN.In this thesis,according to the basic theory of power amplifier design,combined with the harmonic control technique,the output matching of class J and class J^-1mode is designed,and the circuit architecture of class J and class J^-1power amplifier is determined.At the same time,according to the large-signal characteristics of the HBT transistor,an adaptive bias circuit is used to improve the nonlinear distortion of the transistor.Class J and class J^-1power amplifiers designed in this thesis are applied to the new generation WLAN.They work in the 2.4 GHz?2.5 GHz frequency band and adopt a two-stage architecture to improve efficiency on the premise of meeting the requirements of linearity.This two amplifiers are biased at shallow class AB and deep class AB respectively.The transistor area is 384 um~2and 3600 um~2respectively.The overall chip area is 680 um*1600 um.Then,according to the designed circuit structure,ADS software is used for circuit simulation,Cadence software is used for layout drawing,and finally,chips are fabricated.Finally,two high-efficiency linear RF power amplifiers applied to the new generation WLAN(2.4 GHz?2.5 GHz)were developed.One was a class J power amplifier,and the other was a class J^-1power amplifier.At 2.45 GHz,the saturated output power of the class J power amplifier was 29.1 d Bm,and the gain was 28.5 d B.At 40MHz MCS11 test signal and EVM=-35 d B,the output power was 17 d Bm,and the peak efficiency PAE was 31%.And the saturated output power of the class J^-1power amplifier was 30.2 d Bm,and the gain was26.5 d B.When the 40 MHz MCS11 test signal was applied to get EVM=-35 d B,the output power was 22 d Bm and the peak efficiency PAE was 32%.The test results show that the two power amplifiers designed in this thesis meet the requirements and achieved the efficiency improvement,which proves the feasibility of the output matching designed in this thesis.Its significance is to adopt a new matching structure to improve the peak efficiency of power amplifier as much as possible without affecting the linearity of it,which has certain research and engineering value.