Development Of C-band Reconfigurable Linear Phase Receiver Front End

With the rapid development of modern electronic communication industry,the chal-lenge is that the available spectrum resources are becoming more and more scarce,so how to Improving the use of spectrum resources has become to be an important research direc-tion.In order to transmit signals with high quality,it is necessary to achieve good group time delay,so reconfigurable linear phase receiving front-end is of great importance.The objective of this thesis is to develop a C-band reconfigurable linear phase receiver front-end,which consists of two core components: a low-noise amplifier and a reconfig-urable linear phase filter.The two core components are analyzed and studied to develop a receiver front-end that can maintain a good group time delay at the center frequency and in the bandwidth reconfiguration process.In the study of reconfigurable linear phase filter,this thesis adopts the cascade quadru-plet structure and introduces two pairs of transmission zeros for improving the group delay and out-of-band rejection by cross-coupling the source and load,and achieves the tunabil-ity of the center frequency and bandwidth of the filter by loading the varactor diode.The filter is reconfigurable with good group delay.In this thesis,we introduce the CQ structure and the method of introducing zero point by source load,analyze the open-loop structure and the improved structure,and perform the related design optimization simulation to ob-tain a group time delay within ±0.65 ns in 60% passband range.After the linear phase filter design is completed,the variable capacitance diode is analyzed,and the subsequent reconfigurability of the filter is studied and analyzed by loading the variable capacitance diode.Finally,a reconfigurable linear phase filter with a center frequency tuning range of 10% and a bandwidth tuning range of 58% was developed.The return loss of the filter is better than 15 d B,the insertion loss is less than 5 d B,and the out-of-band rejection is more than 20 d B.The other core device is a low-noise amplifier.According to the index requirements of its system,the chip of the amplifier is determined through selection and the related performance of the amplifier is simulated and verified.After completing the circuit sim-ulation,the layout design is processed and finally the assembly test is performed.After testing and passing the index requirements,thus making a low noise amplifier with a gain of 15 d B and a flatness of ±0.7d B,while the noise factor is below 1.8d B,so the overall test data basically meet the design index.Then the low-noise amplifier and the filter are assembled in cascade to obtain a C-band reconfigurable linear phase receiver front-end.After testing,we can get its operating frequency of 4.5-5.08 GHz,center frequency tuning range of 10%,bandwidth tuning range of 58%,and in the reconfiguration process can be in the passband range of 60% group time delay undulation less than ± 0.65 ns,1d B compression point in 16.2d Bm,to meet the design specifications.