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High Power High Efficiency Digital Power Amplifier

Posted on:2022-12-17Degree:MasterType:Thesis
Country:ChinaCandidate:T Y WangFull Text:PDF
GTID:2518306764964059Subject:Wireless Electronics
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With the rapid development of wireless communication,the demand for transmitter systems is increasing greatly.High performance RF power amplifier is one of the key parts of a transmitter system.The performance of RF power amplifier is dominant on the overall performance of transmitter systems.To satisfy the requirement of high power,high efficiency transmitter systems,massive work have been done by researchers.Digital power amplifiers are a new kind of power amplifier.It operates under switching mode,while featuring a high efficiency.Also,the high integration level of digital power amplifiers reduces other modules in transmitter systems.Thus improves the efficiency of transmitter systems further.This thesis focuses on the architecture,circuits,and implementation of polar transmitter system.And investigates the performance of this architecture.Designed a high power,high efficiency power amplifier.In this thesis,firstly the commonly used transmitter architectures are discussed.And lists the pros and cons of them.Also,the rules of operation and waveforms are discussed.Then presents the design flow of high power,high efficiency power amplifier.The number and size of core MOS are determined by required output power.Then the best matching point is simulated.After that,the driver circuit is designed.Then the matching network is designed.Power combining is used to increase output power.What's more,to address the imbalance issue in the matching network,a compensation capacitor is introduced with the help of circuit and EM simulation.The compensation capacitor effectively improves the balance effect of the matching network,thus increases the efficiency.Next,the base band interface and encoder are also discussed.In this thesis,a digital power amplifier based on 40-nm CMOS process is designed and tested.The operation frequency of the designed chip is over 1.2–2.8GHz,with the peak of 32.4 d Bm at 2GHz.The peak drain efficiency of 53.8% is achieved at 1.8GHz.It supports 50 MHz 64-QAM with average output power of 25.37 d Bm,EVM of –26.97 d B,ACPR of –29.61 d Bc,and 10 MHz 1024-QAM with average output power of 22.14 d Bm,EVM of –35.75 d B,ACPR of –35.37 d Bc.
Keywords/Search Tags:Digital Power Amplifier, High Power, High Efficiency, Balance Compensated Matching Network
PDF Full Text Request
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