Research On Unified Hardware Architecture Platform For Wireless Communication

With the development of the times,people's demand for mobile Internet has become more and more diversified.At present,wireless communication is integrating many emerging technologies such as big data,artificial intelligence,Internet of things,AR / VR and so on.All kinds of emerging services have put forward higher requirements for both the real-time computing power of the platform and the transmission capacity of the communication system.In order to solve the problem of increasing data transmission requirements of wireless communication at present and in the future,while taking into account the hardware efficiency,the signal processing platform for wireless communication needs to meet the requirements of high throughput,low delay,high hardware utilization efficiency and certain flexibility.Based on the above requirements,this thesis proposes a unified hardware architecture platform solution for wireless communication from two aspects of hardware and algorithm.Starting from the requirements of wireless communication,this scheme first analyzes the common characteristics of wireless communication algorithms,and designs the vector processing core of the unified hardware architecture platform from the operator level of hardware according to these common characteristics.At the same time,No C is introduced as the data transmission network between different vector processing cores of the common architecture platform;At the algorithm level,the algorithm to be deployed is first disassembled at the operator level,so that the algorithm becomes a directed acyclic graph in the form of task flow graph,and then the disassembled wireless communication algorithm is efficiently deployed to the unified hardware architecture platform through task mapping.The advantages of this solution,which considers both hardware design and algorithm level deployment,are as follows: first,it has high flexibility and can flexibly support the deployment of a variety of wireless communication algorithms without changing the hardware design of the unified hardware architecture platform;second,the hardware utilization is high,the vector processing core is specifically designed at the hardware level,at the same time,the disassembled algorithm is efficiently mapped to the unified hardware architecture platform by task mapping at the software level,the combination of the two makes the algorithm achieve good hardware efficiency on the unified hardware architecture platform;third,the algorithm has high execution efficiency,by disassembling the algorithm at the operator level of the wireless communication algorithm to be deployed,the operator quantity and data flow path of the algorithm are clarified,and the task flow diagram of the algorithm is obtained,then,the disassembled algorithm is mapped to the processing core of the unified hardware architecture platform through the task mapping algorithm,so as to maximize the parallelism of the algorithm and make the algorithm run efficiently on the unified hardware architecture platform;fourth,good scalability,the unified hardware architecture platform adopts the transmission structure based on No C,which can achieve better scalability than the bus structure,when there are high requirements for computing power or new special processing cores need to be added,the seamless connection between the platform and the platform can be realized directly by "building blocks".The unified hardware architecture platform solution for wireless communication proposed in this thesis has been tested and verified on the ZYNQ-7000 So C Platform of Xilinx.Through the complete algorithm transplantation process(algorithm disassembly,task mapping,program writing,algorithm deployment)of two wireless communication algorithms of MIMO and CDMA on the co-architecture platform,the flexibility,high throughput,low latency,and high hardware efficiency of the co-architecture platform for wireless communication algorithms are verified.It has formed a certain reference value for the next research and development of the co-architecture platform.