Design Of Low Noise And High Precision Programmable Gain Amplifier For Accelerometer

With the development of MEMS,the application of various sensors has become more and more complex,so the requirements for front-end signal processing modules have become higher.As the front end of the signal processing unit,the low noise amplifier is responsible for signal extraction and amplification.At the same time,for various sensor application scenarios,the low-noise amplifier also needs to have a gain adjustment function to increase a certain degree of versatility.Therefore,in the design of this thesis,a low-noise programmable amplifier is designed based on CMOS 40 nm for the amplification of front-end signals.As a precision operational amplifier,compared with traditional operational amplifier,instrumentation amplifier have high common mode rejection ratio(CMRR),high gain and flexible gain adjustment function,so it is widely used in sensors,medical devices and high-end audio equipment.However,the traditional dual-op amp instrumentation amplifier does not have the advantage of low noise.For complex application scenarios,the noise will overwhelm the signal.As a result,the signal-tonoise ratio cannot satisfy the system.In order to meet the low noise requirement,an instrumentation amplifier with noise reduction technology is designed in the thesis.Firstly,the basic principles of programmable amplifiers and the indicators to measure the performance are introduced,and two circuit structures are analyzed.Then,two main noise reduction techniques are studied: sampling-based auto-zeroing technology and modulation-based chopping technology is analyzed,and the influence of the two technologies on noise and offset voltage is analyzed.The front-end amplifier used in the sensor mainly amplifies the signal in continuous time,so the circuit design in the thesis adopts the chopping technology.Finally,the specific circuit designed in the thesis is introduced,and a series of techniques are applied to improve the gain,driving ability and stability of the amplifier.In addition to core amplifier,basic auxiliary circuits such as current source,bias circuit and clock are designed to ensure the stability of the amplifier.The circuit designed above is simulated to ensure that the design performance indicators are met under as many simulation conditions as possible,and increases stability.The circuit is designed based on 40 nm CMOS process and verified by tape-out.Since the amplifier and the post-stage 24-bit Sigma delta analog-to-digital converter are integrated on the same wafer,the total chip area is 1.8mm×0.8mm.when the bandwidth is 1KHz,which can provide the pre-drive capability for the 20-bit analog-to-digital converter.