Research And Design Of High Speed Pipelined SAR ADC

The analog-to-digital converter(ADC)is a bridge connecting the analog world and digital devices,and its performance has gradually become the decisive factor for the performance of the analog-digital hybrid system.With the advent of 5G communication technology and the development of the Internet of Things era,higher performance requirements are put forward for high-speed and high-precision ADCs.The successive approximation ADC has the advantage of low power consumption,but the speed is limited by the structure,and the accuracy is limited by capacitance mismatch and thermal noise;the pipeline ADC has the advantage of high speed and high resolution,but the power consumption is large,and the resolution increases every time 1bit,the headroom amplifier has one more stage,and the corresponding power consumption is also doubled.The pipelined successive approximation(Pipelined SAR)ADC combines the advantages of the two to achieve low power consumption while ensuring high speed and high precision,which has become a research hotspot in this field.This article designs a 12-bit 100MSPS Pipelined SAR ADC.First,it introduces the basic principles and structural characteristics of Pipelined SAR ADC,and analyzes its various non-ideal characteristics,such as switches and capacitors.In addition,it analyzes the number of stages and the choice of quantization bits,focusing on the number of stages versus speed.And the influence of power consumption,a two-stage structure of 6+7 is determined;the timing is controlled reasonably,and asynchronous timing is sampled between and within the stages;the first-stage DAC uses a binary capacitor array,the bottom plate is sampled,and the SAR logic uses Vcm-based switching method to avoid charge injection and improve linearity;the second-level DAC uses a binary segmented capacitor array,the upper board samples,and the SAR logic uses a segmented and monotonic hybrid switching method to ensure that the number of capacitors is reduced In this case,the output common-mode voltage is stabilized and the design difficulty of the comparator is reduced;the output swing and gain of the margin amplifier are reduced through the inter-stage attenuation technology,and the design difficulty of the second-stage SAR ADC is reduced;the two-stage SAR ADC Redundant technology is used to reduce the offset error and gain error;a high-order compensated band gap reference is proposed to ensure the stable output of the common-mode voltage.This paper has completed circuit simulation and layout drawing under 180nm CMOS technology.The simulation results show that under 1.8v power supply voltage,when the sampling rate is 100MS/s and the input signal is a full-swing sine wave signal,the effective number of bits is 9.9 bit,the signal-to-noise ratio is 62.55d B,the spurious-free dynamic range is 67.89 d B,the power consumption is 27m W,the core circuit area is 0.132mm~2,and its indicators meet the design requirements.