Circuit Design Of DNN Accelerator For Structure Pruning Compression Algorithm

Deep neural networks(DNN)have achieved very good results in speech recognition,image classification,and face detection.However,on mobile devices that have high requirements for power consumption and real-time performance,deployment of storage-intensive and computing-intensive DNNs is more difficult.In order to solve this problem,DNNs are usually compressed to reduce the amount of model parameters and calculations.Therefore,it is of great practical significance to design a low-power,high-throughput accelerator for deep neural network compression algorithms.In this thesis,summarized the basic structure of DNNs,classic algorithms,and common performance optimization methods for accelerators.For compression algorithms that combine structure pruning and power exponential quantization,a high-throughput,low-power convolutional neural network(CNN)is designed.Firstly,the accelerator architecture is designed by analyzing the factors that affect the accelerator's performance,based on the model,the memory access mathematical model and the highest model are constructed,then optimal parameter combination is selected.Secondly,adopted a parameterized configuration design and three reused modes to reduce the number of memory accesses.Finally,encoded the network parameters after structural pruning and power exponent quantization,and designs a special calculation unit to disassemble the encoded weight.The key circuit functions and simulation verification of the accelerator are introduced in detail.The comprehensive results based on TSMC 40nm process library show that under the conditions of operating frequency of 300MHz and operating voltage of 1.1V,the total power consumption of the hardware accelerator circuit is 0.14W,the overall accelerator area is 8.22mm~2,and the actual average throughput rate is relative to Alex Net and VGG-16 are 213.21GOP/S and240.05GOP/S,respectively,the peak throughput rate is 268.8GOP/S,and the energy efficiency ratio is about 1.92TOPS/W.Compared with accelerators such as EIE,Cambricon-X and Ze NA,the area and energy efficiency ratio of this paper have been improved by 4.0?7.0×and 1.6?3.3×,respectively.Using the Zynq-7100 development board as the implementation platform,under the condition that the operating frequency is 200MHz and the VGG-16 is used as the test network,the measured accelerator power consumption is 2.854W,the average throughput rate is 160.48GOP/S,and the energy efficiency ratio is 57.3 GOPS/W.The accelerator oriented to the structure pruning compression algorithm designed in this paper has certain reference significance for the research and design of lightweight and low energy consumption of artificial intelligence terminals.