Research And Implementation Of Time Synchronization For 60GHz MMW Communication System

The millimeter wave frequency band contains abundant and unlicensed spectrum resources,mak-ing millimeter wave communication technology gradually become a hot research direction.However,the inherent high attenuation propagation characteristics of millimeter wave signals limit its main application to indoor communication scenarios,and the significant frequency offset and ultra-high symbol rate brought by high frequency and wide spectrum also make the realization of millimeter wave communication systems difficult.challenge.Timing synchronization,as an important stage in the wireless communication system,assumes the responsibility of providing time reference for the receiver processing process.Faced with the extremely high symbol rate in the millimeter wave communication scenario,stable and efficient timing synchronization is to ensure the communication system Basic requirements for normal work.In this article,it mainly introduces the algorithm research and hardware implementation for the timing synchronization of the 60 GHz millimeter wave system using the IEEE 802.11ay stan-dard frame structure.Timing synchronization consists of frame synchronization and symbol timing synchronization.Based on the simulation analysis of some classic algorithms,two schemes suit-able for this system and capable of realizing hardware structure multiplexing are designed.Correla-tion schemes and autocorrelation schemes with strong stability.Among them,the cross-correlation scheme uses Ga₁₂₈sequence cross-correlation as the preamble detection algorithm,and differential cross-correlation as the symbol doundary detection algorithm.In the synchronization process,only one set of parallel cross-correlators is reused.Two-stage functions can be realized.The autocorre-lation scheme uses the S&C algorithm as the preamble detection algorithm,the parallel dual-mode autocorrelator completes the two-stage autocorrelation operation,and uses the phase reversal algo-rithm as the symbol doundary detection algorithm,which can use peak detection and phase detection to perform high Symbol boundary positioning for stability.When the SNR of the two schemes is greater than 10 d B in the CM3 channel model,the probability of synchronization failure can be re-duced to less than 10^-3.The final hardware circuit simulation test results show that both schemes can operate normally as designed when the signal-to-noise ratio is 15 d B.After synthesis,the timing synchronization hardware circuit consumes up to 2%of the logic resources of the FPGA chip,and the DSP resource occupied within 1%,and the maximum clock rate can reach 430.29 MHz.The hardware circuit saves hardware resources and meets the clock requirements,while also ensuring the normal operation of the system timing synchronization function,and has a wide range of application prospects.