Block-based Path Delay Modeling And Verification At Low Voltage

Under the background of low-voltage advanced process integrated circuit design,the method of design process collaborative optimization(DTCO)is proposed,timing analysis plays an important role in the DTCO method.The main research point of the thesis is the timing analysis problem in low-voltage design.The distribution of circuit delay generated by process parameter fluctuations at low voltages has non-Gaussian characteristics,so that the traditional delay models based on Gaussian computations could not work well and the"gold standard"based on Monte Carlo(MC)simulation is becoming increasingly unacceptable due to the huge time-consuming.In order to solve the time-consuming problem of MC and considering the influence of process parametric variations on the circuit delay under low voltage and based on the ideas of block-based statistical static timing analysis(SSTA),this thesis explores the accurate and fast statistical modeling methodology which exploits a set of statistical parameters like mean as well as standard deviation to represent timing behavior characteristics for the combinational logic circuit.The error compensation model established by multiple regression methods is applied to the single-input and dual-input nodes in the circuit.Based on the existing SUM and MAX/MIN operations,this model adds an error compensation term to the mean square error of the output delay of the single and dual input nodes;when one input of the dual input node is fixed,it is first equivalent to a single input node.Enter the nodal model,and then perform error compensation on its mean square error.This article further simplifies the error compensation model based on multiple regression.By screening the key parameters in the calculation of the three models,the regression coefficients are reduced,and the modeling speed of the model is accelerated.The~2 evaluation method is used to verify the fit of the empirical data.This method improves the accuracy of the model.The experiments of the thesis all use the SMIC 28nm process library to verify the path delay model proposed in the thesis under the voltage condition of 0.6V.The verification circuit uses 8 test circuits in the ISCAS 85 test set.The circuit includes inverters,NAND gates,and three basic units of NOR gate.Experimental results show that,compared with Monte Carlo simulation,the average error of the path delay model in this paper is 0.41%,the average error of standard deviation is 4.28%,and the average time is about 1/430 of the Monte Carlo simulation.Compared with Jennifer's method,the accuracy is improved by 45.36%at the same speed.