Design Of Orthogonal VCO And BGR Integrated Circuit In 25Gbaud/s PAM4 Clock Data Recovery

High-speed serial communication has been increasingly used in fields such as communication networks and computer systems because it saves transmission media and can achieve asynchronous transmission.The data clock recovery circuit(CDR)is a core module of high-speed serial communication,and its performance determines the performance of the entire high-speed serial transmission system.The voltage-controlled oscillator(VCO)is the key module of the CDR.The band gap reference(BGR)can provide a high-performance reference voltage,and its accuracy has a direct impact on the performance of the CDR.Therefore,the research work of this dissertation has important significance and value.In this dissertation,the design of the quadrature VCO and BGR circuits in 25Gbaud/s PAM4 CDR is completed in 40 nm CMOS process.The performance indicators of the quadrature VCO include tuning range,orthogonality,phase noise and power consumption,while the performance indicators of the BGR include temperature drift coefficient,power consumption and power supply rejection ratio.The quadrature VCO is realized by the parallel coupling of two identical inductor-capacitor oscillators(LC-VCO)and a single LC-VCO adopts a fully differential complementary cross-coupling structure.The BGR circuit is used as the reference voltage of the front-end comparator in the clock data recovery circuit,and is realized by a voltage-mode structure.The layout size of the quadrature VCO circuit designed in this dissertation is400?m×180?m.The post-simulation results show that at TT corner and 27?,the tuning range of the quadrature VCO is 10.71GHz?13.69 GHz,the orthogonality reaches 88.2°,and the phase noise at 1MHz is-97.65 d Bc/Hz,the power consumption is 6.27 m W.The temperature drift coefficient of the BGR is 15.44ppm/?,the power consumption is 0.68 m W,and the power supply rejection ratio at low frequency is-56.57 d B.The post-simulation results of various indicators meet the original design goals,and there is a certain margin.