| Chip technology occupies a strategic,basic and leading position,which is related to citizen information security and even national defense strategy security.At present,my country’s chip industry basically purchases X86 or ARM instruction set architecture authorization from foreign chip technology companies for secondary research and development.With the turmoil in the international situation in recent years,the United States has frequently issued "chip sanctions" against my country,resulting in many reliance on chips.Developers who pay high licensing fees can’t use these two technologies,and are stuck in a life and death situation.my country must look for new technological breakthroughs and design independent and controllable chips from the open source instruction set architecture to meet this challenge.Both the LLVM compiler framework and the RISC-Ⅴ instruction set architecture are popular open source technologies,and the research and development based on them has received more and more attention.One of the problems currently facing the RISC-Ⅴ architecture is the development environment.The maturity of the development environment,especially the compiler,directly affects the number of users of RISC-Ⅴ and the scope of its application.Binary file code density is one of the important indicators to measure a chip,especially the development environment of embedded chips,and its degree of optimization directly affects the area and cost of embedded chips.This article combines the features of LLVM compiler and the RISC-Ⅴ instruction set to study the code density of the binary files generated by it.After a large number of benchmark tests,it is found that the current RVC compression instruction set designed in the RISC-Ⅴ instruction set is not perfect enough and the LLVM compiler register cross-function call allocation method.Aiming at the problem of unreasonable register allocation of the RISC-Ⅴ architecture,the paper addresses the above problems.Carrying out related optimization algorithm research work,the main tasks completed are as follows:1.The improvement strategy of RVC compression instructions is proposed.The basic idea of ??the RVC compression instruction is to express the 32-bit coded instruction with 16-bit code to reduce the code size of the assembly instruction in the binary file generated by the compiler.Due to the particularity of the RVC instruction encoding,during the test,it was found that there are still some codes that can be compressed but do not meet the current RVC instruction encoding.After careful study of these uncompressed RISC-Ⅴ instructions,they are divided into immediate number addition,There are four categories of jump control transmission,branch control transmission and data transmission instructions.For each type of uncompressed instruction,a corresponding 16-bit compressible coding improvement strategy is proposed.(1)For the immediate addition instruction operation,two compression instructions are designed.The C.LI* instruction can load the zero-extended 8-bit immediate data into the register rd’,and the C.ADDI* instruction can extend the non-zero sign The 11-bit immediate data is scaled by a multiple of 2 and added to the value in register a5,and then the result is written into register a5.(2)For the conditional jump instruction operation,the C.J* instruction is designed to reference the linker symbol table to calculate the target jump address so that the jump operation can use the index or pointer to index it into the address table and retrieve the address.(3)For branch control transmission instruction operations,two compression codes are designed.The C.BEQBNE instruction can perform conditional control transmission bne or beq operations according to the selected bit.At the same time,the offset zero extension is scaled by a multiple of 2 and added to PC to form the branch target address;C.BRANCH instruction is executed by the sb function(bne,beq,blt or bge)The specified condition controls the transfer,and the offset zero extension is scaled by a multiple of 2 and then added to the pc to form the branch target address.(4)For the operation of data transmission instructions,two compression codes are designed.The C.LDSTBYTE0 instruction can be executed according to the selected bit.Load the 8-bit unsigned value from the memory to the register rd or store the 32-bit value from the rs2 register to the Memory,and then retrieve the effective memory address by reading the base address in the register rs1;the C.LDSTWORD0 instruction can be executed according to the selected bit to load the 32-bit unsigned value from the memory into the rd register or the 32-bit value from the rs2 register Store to the memory,and then retrieve the effective memory address by reading the base address in the register rs1.The test results show that the optimized RVC instruction set encoding can increase the binary file code density by about 7%.2.A new register allocation algorithm RAIBCD is proposed.It has been optimized and improved on the premise of the LLVM compiler register allocation linear scan algorithm on the existing RISC-Ⅴ platform.First,an active variable register allocation cost model is proposed,and then according to the cost code,the register allocation algorithm for cross-region active variables is optimized,Proposed and designed and implemented the RAIBCD algorithm,thereby reducing the number of instructions generated by the compilation and increasing the density of the generated binary code.It can be seen from the test results that the density of the binary code file generated by the compiler after the RAIBCD algorithm is enabled is significantly increased by about 10%.3.Using the benchmark tool CSi BE,the code density optimization experiment and analysis were carried out.The test results show that the LLVM compiler adopts both the RVC instruction improvement strategy and the RAIBCD register allocation algorithm designed in this paper,which can increase the code density of the generated RISC-Ⅴ binary file by about 15%,which proves the reliability of the two optimization and improvement strategies proposed in this paper. |
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