Research And Design Of Phase Locked Loops Based On FPGA

With the connection of new energy power generation systems such as wind and solar energy into the grid,grid synchronization technology has become increasingly important.Phaselocked loop(PLL)is a key technology for grid synchronization,and it must have good dynamic performance and anti-interference.At present,the phase-locked loop based on quadrature signal generation(QSG-PLL)is an important research direction of phase-locked loop algorithm.Among them,the phase-locked loop based on the second-order generalized integrator(SOGI-PLL)is more popular,with good dynamic performance and phase-locking accuracy.In order to obtain dynamic performance similar to SOGI-PLL and improve the anti-interference performance of the phase-locked loop,from the perspective of modern control theory,this paper proposes phase-locked loops based on the luenberger observer(LO-PLL and LO-DC-PLL),mainly for harmonics and DC,and compares the performance with SOGI-PLL.1)LO-PLL structure.Theoretical research shows that the attenuation rate of the integral link is always-20 d B/dec,Therefore,it is considered to add the integrator as a pre-integrator to the LO structure to improve the harmonic suppression capability of the LO structure,and thus the LO-PLL structure is proposed.Compared with SOGI-PLL,the simulation results show that LO-PLL has dynamic performance similar to SOGI-PLL,and the harmonic suppression capability has also been improved.2)LO-DC-PLL structure.In order to effectively eliminate DC,a power grid model containing DC components is established,and the DC disturbance signal is introduced as a state variable into the LO-DC observer,and the LO-DC-PLL structure is proposed.Comparison and simulation with SOGI-PLL show that LO-DC-PLL has enhanced harmonic suppression capability and can eliminate DC component on the basis of similar dynamic performance as SOGI-PLL.In terms of the realization of the phase-locked loop algorithm,due to the advantages of field programmable gate array(FPGA),such as good reliability and fast calculation speed,this article implements the phase-locked loop algorithm based on FPGA.Firstly,the design scheme of key arithmetic modules is given,including the low-level implementation of 32-bit signed fixed-point decimal multiplier and integrator,and the generation of different digital signal sources.Then,FPGA implementation schemes of PLL structure,SOGI-PLL structure,LO-PLL structure and LO-DC-PLL structure are given respectively.Finally,through FPGA experiments,their performance is compared and verified to verify the correctness of the theory.This verifies the reliability and effectiveness of the FPGA arithmetic module independently designed in this paper,and has certain reference significance and research value for the realization of phase-locked loop algorithm based on FPGA.