Research On Frequency Offset Estimation Algorithm And Its FPGA Implementation

Clock frequency deviation between the transmitter and the receiver will degrade BER and performance of the communication system.In order to reduce the impact of frequency offset on communication system,frequency offset estimation and correction in digital communication has become a key issue.This thesis studied the basic principle of parameter estimation and frequency offset estimation theory.The estimation range and accuracy of classic frequency offset estimation algorithms were simulated.Advantages and disadvantages of frequency offset estimation algorithms are analyzed and some improvements are proposed.By the study on carrier synchronization for OQPSK and burst OQPSK modulation,a novel implementation scheme for M&M frequency offset estimation algorithm based on FPGA is presented in this thesis.By transforming parallel to serial calculation and adopting the dual port RAM,the hardware resource consumption is reduced greatly.The simulation results are very close to the outputs of frequency offset estimation hardware module.The hardware implementation has proved to be high-accuracy and wide estimation range.According to 802.15.4 protocol signal model,and combined with frequency offset estimation algorithms,a novel carrier recovery scheme of 802.15.4 protocol is implemented on FPGA.The scheme includes modules of frame starting detection,frequency offset estimation,initial phase estimation and residual frequency offset estimation.The implementation improvement include hardware optimizations for auto-correlation calculation,adoption of pipeline Cordic algorithm for frequency offset estimation,hardware logic reuse for phase and residual frequency offset estimation,and dual port ROM based NCO.Finally,test signals with frequency offset are used for testing the performance of the hardware implementation,experimental results demonstrate the effectiveness of the proposed hardware implementation scheme for carrier recovery.