The Design Of Multi Channel DMA Controller Based On New AHB Bus Architecture

Direct Memory Access(DMA)technology is an important high-speed data transmission technology in the field of modern storage.Before data transmission,the Central Processing Unit(CPU)initializes the configuration of the DMA controller.After that,the DMA controller can independently complete the data transmission operation between the corresponding storage devices according to the configuration information without the need for CPU participation,thus alleviating the pressure on CPU resources and greatly improving the system performance and data transmission speed.With the development of So C(System on Chip)system scale,the efficiency of data transmission between different memory peripherals directly affects the performance of the system,the single-channel DMA controller has obviously been unable to meet the requirements of the system,so the research and development of multi-channel DMA controller has become very important and urgent.In view of the actual project requirements,based on the new bus-matrix system architecture,an 8-channel DMA controller using dual AHB(Advanced High-Performance Bus)master bus structure and independent FIFO(First Input First Output)cache is proposed.Each channel has an independent 4-word depth FIFO buffer and can manage 8peripheral transfer requests,which means that the DMA controller can handle up to 64 peripheral transfer requests at one time.The highlight of this design is that each channel of DMA controller can realize independent transmission configuration,and a programmable channel priority design is proposed for multi task burst transmission,implement a high-priority task priority transmission arbitration mechanism,at the same time balancing the fair principle of multitasking transmission,eight channels in the round of transmission in priority order all on a burst transport,the next burst transfer of priority is then started until all channel transfer tasks are completed.Compared with the single-channel DMA controller,this design does not need to reinitialize the configuration of the DMA controller every transmission,and can manage multiple peripheral transmission requests with different priorities at one time,improving the data transmission rate and flexibility of the system.According to the content of the design,this paper studies and summarizes the AHB bus protocol and DMA data transmission method.Based on the multi-layer and efficient on-chip matrix bus system architecture,the overall design plan of a fully functional8-channel DMA controller is developed,and the function realization mode of DMA controller is emphatically analyzed.Each module is divided according to the functional structure,including data flow module(which is divided into channel selection module,FIFO module and mode control module),arbiter module,memory port module,peripheral port module and register configuration module,etc.Then the RTL(Register Transfer Level)behavior description of each sub-module and the top instantiated module is realized by Verilog hardware design language.After the completion of the design task,a verification platform was built independently,and simulation test files were written.Using electronic design automation software tools to compile the design code and perform simulation verification of the front-end functions of the sub-modules and the top-level module.Finally,through verification,each module of DMA controller works normally,realizes the key functions such as channel priority polling arbitration,burst transmission and 8-channel independent configuration,and the simulation waveform display is correct.The data transmission task from the source end to the destination end is successfully completed,which meets the design requirements of the project.