Design Of Multi-camera Array Image Display And Storage System

With the rapid development of digital image technology,imaging systems are required to have a larger field of view,higher resolution and total pixel value in aerospace,defense industry,telemetry remote sensing and other applications.Traditional single-camera imaging systems often have small field of view,low resolution and limited information to meet the demand.Therefore,multi-camera array imaging system has become an effective solution,which has received wide attention and development in recent years.At present,similar systems fail to achieve a good balance in performance,functional completeness,development cost,expandability,secondary iteration,etc.Based on the above factors,this thesis puts forward an optimized system design scheme for real-time display and image storage applications of large field of view HD images,such as wide-area monitoring,ground shooting,public security,etc.The system puts forward the design idea of "multi-cascading,step-by-step control",which supports ten camera arrays with a resolution of4000×3000@20fps to connect to the system,and uses a variety of FPGA chips and Nvidia's system module Som Jeston TX1 to realize low-cost large data image acquisition,transmission,display and storage.The system has the characteristics of high processing performance,strong expandability,efficient development iteration and convenient maintenance,and is equipped with corresponding upper computer software,which supports the efficient deployment of image processing algorithm,and has good application value.The main contents of this article are as follows:(1)To analyze the current situation of multi-camera array systems at home and abroad,and to determine the design ideas and overall design schemes of the system by comparing their advantages and disadvantages.The scheme divides the system into five subsysyscies of upper computer,master control,forwarding,front end,interconnection and connecting step by step,with independent control and processing units at each level except the interconnect subsyscies.This design reduces system complexity,clear structural and functional boundaries,maximizes hardware resource utilization,reduces development,maintenance and iteration costs,and improves system scalability and system image processing performance.(2)To clarify the specific design and functional tasks of each subsyscies divided into the overall design plan.The upper computer subsyscies provide software and interface on the PC to complete the display of various functions control and function effects,the master subsyscies include Jeston TX1 and master FPGA,complete the software and hardware information interaction and system information distribution control,the forwarding subsysyscies use forwarding FPGAs to complete information routing and expand the interface connecting the front end of the camera,the front terminal system uses two frontend FPGAs to complete the acquisition,processing and storage of camera data,and the interconnection subsyscies provide intersysc system connection schemes and transmission protocols.(3)According to the design of a reasonable hardware platform,the circuit schematic design of different subsysysms,PCB layout wiring and device selection work.Finally,the design and production of data master circuit board,data routing circuit board,CMOS circuit board,data processing circuit board,data storage circuit board 5 types of hardware circuit board.(4)Complete the implementation and code development of the specific function modules of the subsyscies,including Qt-based upper-level software development,C/C-based Jeston TX1 development,and Verilog HDL-based FPGA development.The main contents include computer software,Jeston TX1 information control processing,PCIe communication transmission,DDR3 SDRAM read and write control,Serdes high-speed data transmission,synchronous serial send and receive,camera SPI dynamic configuration and serial reception,eMMC read and write control,etc.In addition,considering all aspects of the system optimization,a custom inter-board transfer protocol,instruction control set,hardware file system,parallel high-speed storage and other optimization schemes are designed.(5)Complete the test work of the system,including circuit testing,device testing,transmission testing,functional testing,resource power consumption analysis.The functional correctness and related performance of the system are tested and analyzed,the system is summarized and analyzed,and the shortcomings are put forward,and the methods of improvement and optimization are put forward.