AER-based Low-power Dynamic Vision Sensor Chip Design

In today's society,with the continuous advancement of technology,machine vision is increasingly replacing humans in acquiring visual information and helping humans deal with complex real-life environments.Machine vision acquires image information through an image sensor,converts the captured optical information into electrical signals,and the electrical signals are processed to represent the grayscale information of each pixel,and the image is reconstructed by the grayscale information in the later stage.The traditional CMOS image sensor outputs image information at a fixed frequency based on the frame and exposure time,so it has the disadvantages of large data volume,large processing delay,large noise,and low dynamic range when performing back-end processing in machine vision.In order to make machine vision more inclined to the visual system of the human eye,a dynamic vision sensor(Dynamic Vision Sensor,DVS)that mimics the working mechanism of the biological retina has appeared.DVS only captures the dynamic information of the image,and converts the change of external light intensity information into event pulses for subsequent processing,so it has the advantages of fast response speed,low delay,sparse image and large dynamic range.DVS further improves the performance of machine vision,and can be applied to the detection and recognition of high-speed moving targets,automatic driving and other fields.This chip is composed of pixel array,row/column wire-or circuit,row arbitration circuit,row encoding circuit,and column readout circuit.The pixel circuit generates a corresponding event when the external light intensity information changes.The wire-or circuit,the row arbitration circuit,the column readout circuit and the encoding circuit select the pixel with the event and the location of the pixel is expressed through the address-event representation(Address-Event Representation,AER)protocol output to the outside of the chip to realize the asynchronous communication of the chip.In this paper,a novel group pixel module circuit is proposed.Group pixels grouped by four adjacent pixels can not only filter possible noise events,but also reduce the processing scale of subsequent circuits,thereby reducing circuit power consumption.A three-input average arbitration circuit is adopted to ensure that the row arbitration circuit only selects one row at a time when the row request signal is sent by the three-row circuit at the same time,and the priority of each selection is rotated in turn.The column readout circuit using fast search outputs the column address of the selected group of pixels and the ON/OFF events information of each group of pixels in each clock cycle,without redundant clock cycles,the problem of large delay in DVS using twodimensional arbitration is solved.Based on the design of the chip system block diagram and sub-module circuit design,this paper uses 0.18 um CIS technology to simulate and verify the sub-module circuit and the overall circuit through the Cadence simulation software platform,and the pixel array is 8×6.The overall circuit has undergone subsequent layout design and post-simulation verification.The simulation results show that the dynamic range of this chip is 101 d B,the contrast sensitivity is 35%,the fill factor is 12%,the overall power consumption of the chip is39.41 u W,and the average power consumption per pixel is 0.821 u W,and the chip can handle every second the number of pixels is 200 M,and the performance indicators of the circuit meet the design requirements.