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Design And Implementation Of Time Synchronization Scheme For Broadband Micro-power Communication System

Posted on:2022-02-15Degree:MasterType:Thesis
Country:ChinaCandidate:F T SuFull Text:PDF
GTID:2518306575468864Subject:Electronics and Communications Engineering
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The broadband micro-power communication system will become an important communication network for the collection and maintenance of electricity consumption information for smart grid users.As a large-scale,self-organizing,tree-type multi-hop network,the research and implementation of time synchronization schemes for broadband micro-power communication systems are very critical.Combining the network characteristics of broadband micropower using beacon mechanism,time division multiple access,and real-time dynamic changes,through the analysis of three classic time synchronization algorithms and key influencing factors,this paper designs a method based on the flooding time synchronization protocol(FTSP)Time synchronization system scheme BMP?FTSP for broadband micro-power communication system:1.Using the beacon mechanism of the broadband micro-power communication system,a method for synchronization through any synchronized node is designed without relying on the same node,which enhances the stability of the dynamic network.In addition,the method of dynamically allocating beacon time slots through CCO can effectively eliminate redundant synchronization paths under the premise of ensuring the synchronization of the entire network and the addition,deletion,and modification of dynamic nodes,eliminating the time delay of channel access,and reducing The complexity of the algorithm and the energy consumption of the system are improved;2.In view of the sources of time synchronization errors:(1)For the delay error of channel access,it is combined with the beacon time slot,and a guaranteed time slot is used to eliminate the uncertain delay of channel competition;(2)To avoid software time stamping In order to achieve higher accuracy,the method of hardware time stamp is adopted to move the time stamp mark and acquisition down to the hardware to complete;(3)For the uncertainty caused by interrupt processing,system processing,and signal propagation Time delay,using a weighted least squares estimation algorithm.Experiments show that the weighted least squares estimation can respond faster,and the synchronization convergence speed is 2 cycles faster on average;(4)In the frequency offset processing,this thesis adopts the frequency offset correction based on symbol synchronization,and the experiment shows that the frequency offset correction Afterwards,the overall synchronization will last longer,and the frequency offset fluctuation will be smoother in both single-hop and multi-hop scenarios;(5)For multihop error accumulation,a dynamic synchronization path scheme is adopted to dynamically select the best synchronization node to reduce multiple levels The number of synchronization hops under.3.In terms of stability,the process of time slot estimation is added to improve the shortcomings of FTSP that cannot adapt to dynamic networks,so that nodes can still maintain multiple cycles of business when the agent changes or the synchronization information is not received in a certain cycle.Next,in the design and implementation of the broadband micro-power time synchronization system,the software and hardware co-design method is adopted,and the hardware function module and interface design are completed through multi-register control by using the characteristics of software and hardware resources.The software module implements the beacon cycle planning module,time slot allocation module,PCO/STA frequency offset correction module and other functional modules and interface design according to the functional structure characteristics.Finally,a customized FPGA development board was used to build a broadband micro-power communication system test and verification platform.Tests have verified that when the network scale is 15 levels and 80 nodes,the system can effectively reduce synchronization frames by more than 50%.The number of synchronization hops in the last stage can be reduced by about 5 hops,and the synchronization error can be reduced by an average of 3 microseconds.The measured results show that the BTS jitter of the system is less than 0.15 microseconds,and the synchronization error of the 15 level is within 20 microseconds,which fully meets the time synchronization index requirements of the broadband micro-power BTS jitter is less than 0.25 microseconds and the synchronization error is within submilliseconds.
Keywords/Search Tags:Time synchronization, Broadband Micro-power, FTSP, Dynamic time slot allocation
PDF Full Text Request
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