Two-dimensional Localization Data Prefetching For On-chip Cache

Data prefetching reduces the on-chip cache data access misses by placing data in the on-chip cache in advance,thereby reducing the processor's waiting time.The existing onchip cache data prefetching technology uses a single-dimensional localization method to group global data streams,and then uses different models and algorithms to predict future access.However,a single-dimensional localization cannot cover all memory access patterns of the program,and a combination of multiple-dimensional localization can make the prefetcher cover more memory access patterns.Due to the limitations of single-dimensional localization,a two-dimensional localization data prefetching technology with on-chip cache is proposed,which combines instruction localization and spatial localization.In the instruction dimension localization,by analyzing the data flow under the same instruction,the historical increment of the data flow is compressed into a tag value,and it is correlated with the corresponding next increment,and the observed instruction memory access pattern is recorded.In terms of spatial dimension localization,the timely offset of the same physical page is obtained through delay processing,and it is associated with the corresponding instruction,and the observed spatial memory access pattern is recorded.The prefetching requests of two localization patterns are generated by the instructions.Finally,the prefetching requests of two localization patterns are combined and prefetched.The experimental results using the Champ Sim simulator show that the twodimensional localization data prefetching technology captures more memory access patterns than other data prefetching technologies,and achieves a higher coverage rate on LLC than other data prefetching technologies.Compared with the previous best-performing data prefetching technology,the performance is improved by 3.89%-17.21% on average.