Spatio-Temporal Data Prefetching

Data prefetching has been a very effective technique to alleviate the effects of the memory wall, and is likely to remain so in multi-core systems. There are many prefetching mechanism which operates by identifying patterns and correlations in the stream of miss address. Spatial correlation exploits access patterns which occur in repetitive spatial acts and temporal correlation exploits repetitive miss sequences. An weakness of temporal correlation is that it can't predict compulsory miss and an fault of spatial correlation is its inability to capture pointer-based dependence while it is very common in the codes. This paper trys to combine temporal correlation and spatial correlation.Based on the analysis of the temporal correlation and spatial correlation of miss addresses and the studies of some data prefetching techniques, this paper proposes a spatio-temporal data prefetching mechanism. It modifies the structure of Global History Buffer and adds the structure of Local Delta Buffer, so it can use spatial correlation to prefetch when the spatial locality is strong, and in contrast, it uses temporal correlation to prefetch. The proposed mechanism can capture regular spatial data access patterns and repetitive data access patterns which span large space.The proposed mechanism is also suitable for chip multiprocessors. In multi-core systems, because multiple threads usually operate on similar sets of data and instructions and threads migrate among multiple cores, the miss addresses of multiple cores often have some spatial correlation and temporal correlation. In order to use the correlations among multiple cores, this paper brings in inter-core cooperative data prefetching which exploits inter-core correlation once it don't find intra-core correlations .This paper uses SESC as simulation environment and the experimental results indicate that the proposed mechanism significantly improve the performance of system. It gets 26% speedup for uniprocessor when running SPEC2000 FP and gets 12.6% speedup for chip multiprocessors when running SPLASH2 .Meanwhile, compared with C/DC, it improves performance by 3.8% .