Research On Modulation Algorithm For FPGA-Based Digital Radio Frequency Transceiver

In recent years,the all-digital transceiver based on field programmable gate array(FPGA)gets more and more attention due to its high flexibility,reprogrammability,and reconfigurability.In FPGA-based all-digital radio frequency transceiver,the multi-gigabit transceiver hard core can only transmit and receive single-bit signal.Therefore,the digital transmitter performs pulse modulation algorithm on the digital transmitted signal for bit reduction,and the receiver generally uses natural-sampling double-edge pulse-widthmodulation(NDEPWM)to sample the analog received signal as a 1-bit sequence.To improve the transceiver performance,this paper conducts a deep research on the modulation algorithm of single-band transmitter and dual-band receiver.For single-band transmitter,this paper proposes an improved mapping-based pulse-width-modulation(MPWM)algorithm,which reduces the implementation complexity and improves the carrier frequency agility of transmitter.As for dual-band receiver,this paper optimizes NDEPWM to reduce the harmonic interference in received signal.The innovations of these two works are:(1)Improved MPWM modulation algorithm: First,it removes Delta-Sigma modulation,reducing the implementation complexity.Second,it removes the traditional digital up-converter and degrades the ratio of interpolations,which reduces the computing resource consumption of FPGA.Third,the carrier frequency of the transmitted signal can be easily adjusted by switching look-up tables,implying higher flexibility.The FPGA measurement results show that,as for 5 MHz signal bandwidth,the error vector magnitude of the improved algorithm can be lower than 2% at all carrier frequencies,and the signal-to-noise ratio can be higher than 45 dB at most of carrier frequencies and its maximum can reach 49 dB.(2)Reference frequency optimization algorithm for dual-band NDEPWM modulation:First,it can prevent high-power harmonics from aliasing with the received signal,which reduces the error vector magnitude of the received signal.Second,the clean bandwidth of the received signal can be set through the algorithm parameters.Third,it is suitable for any carrier frequency and signal bandwidth.The FPGA measurement results show that,the proposed algorithm can help to improve the error vector magnitude and clean bandwidth for any carrier frequency.The error vector magnitude can increase up to 2.77% for 5 MHz signal bandwidth.And the clean bandwidth can be flexibly adjusted by setting different values for the algorithm parameters.