Study On Secure And Reliable Active IC Metering Technology

Nowadays,the business mode of ICs is mostly the joint mode of fabless and foundry companies.The cooperation between the two parties enables them to share not only the responsibilities for the high cost due to research and development of advanced technology,but also the encountered risk.However,the manufacturer can obtain the designer's layout and netlist,but the designer does not know the details of the backend of the manufacturing process.Under this case,the design company outsources the IC to a foundry oversea,which may lead to IC overbuilding.On one hand,IC overbuilding will cause huge economic losses to IC owners.It is reported that due to overbuilding,IC designers lose billions of dollars every year.On the other hand,it rouses a series of security problems.In particular,when chips contain sensitive information and the overbuilt chips are shipped to adversary,it may cause a catastrophe in related fields.In order to realize the monitoring and control of the production of chips,IC metering technology came into being.For existing external active metering solutions,the PUF design is required to provide a unique ID for each chip.However,the reliability and stability of existing PUF designs are not ideal.The reliability of PUF directly affects the authentication process.IC metering also need logic locking to protect the design by adding some circuit/gate associated with the key to the original design.But it has been found that the lock on the combinational paths is vulnerable to the attack based on satisfiability(SAT)checking,so there are major security issues.This paper proposes a reliable PUF design based on SR-Latch to solve the problem of insufficient reliability of PUF.Theoretically,the output of the SR latch is random two symmetric input signals of the SR latch simultaneously jump from the forbidden state to the opposite state.And the output has three situations,which are stable ‘0',stable ‘1',and metastable state.Based on the output characteristics of SR latch,we propose a PUF design based on SR-Latch.However,metastable behavior will affect the reliability of the design.To reduce the possibility of metastability,SFFs are introduced to the two input terminals of the SR latch to increase the delay difference between the two symmetric signals.Then the output of the SR is sampled multiple times by the multi-sampling circuit to identify metastable latches,for which the output will be determined by the output of the XOR operation of the two counters.One counter represents the sequence number of the latch in all latches,and the other counter represents the order of the latch in all latches that produce metastable state.In the case of unstable behavior occurring in a small number of stable latches,additional stable latches are introduced to replace them.The proposed design has been implemented in the Xilinx Virtex-5 FPGA board.The experimental results show that this design has excellent uniqueness and randomness.The reliability can reach 100% when the temperature varies from 25 ? to 85 ?.The repeatability of PUF is as high as 100%.The proposed design accounts for only 1.72% of the LUT and 0.89% of the registers,introducing only a small area overhead.To resist SAT attack,in this work,the scan design is locked by introducing a double locking design to prevent an attacker from getting the correct information from the scan chain.In order to prevent the untrusted entities from receiving the correct data without a correct key in the normal working mode of scan design,the normal data input is obfuscated to complete the sequential logic locking scheme.And a 2-to-1 multiplexer is added before N randomly selected scan cells.In order to impede the unauthorized manufacturer from accessing scan data normally from the output terminal of scan chain,and in order to achieve secure extraction of PUF responses,an obfuscated circuit is inserted in the output of N randomly selected scan cells(the scan cells selected for sequential lock can be reused here).The dual locking design not only realizes the security extraction of PUF response,but also effectively limits the controllability and observability of the internal scanning unit,thus effectively defending against SAT attacks.In addition,it can also prevent reverse engineering and resist typical attack methods,such as side-channel attacks,bypass attack,etc.The proposed PUF design and logic locking scheme are used to achieve reliable and secure active external IC metering.The area overhead introduced in the whole design is equivalent to 3660 NAND gates.In the existing IC metering scheme,the area overhead of the proposed scheme is the minimum among all the compared methods.