Study On The Electrical Characteristics Of Power Integrated Devices Under Mechanical Strain

As is known to all,strained silicon technology is capable of improving carrier's mobility and is regarded as one of the key technology to optimize the performance of semiconductor devices.Since the first application of strained silicon MOSFET in the 1990s,strained silicon technology has been considered as an indispensable element in modern CMOS technology although its development is relatively slow in power devices field.Typical representatives in power integrated devices(LDMOS,LIGBT)have inverted channel regions and the drift regions as the conduction paths.The inverted channel regions and drift regions have completely different strain effects,which absolutely complicates the strain effects in power devices.From the perspective of practical application,the power integrated device is manufactured by the Bipolar-CMOS-DMOS(BCD)process,which is compatible with the strained silicon process.Therefore,in order to introduce strained silicon technology into power integrated devices,it is extremely important to study the electrical performance of LDMOS and LIGBT under mechanical strain.Herein strain is introduced into the device by bending the silicon wafer,thereby avoiding the impact of processes and structural changes.Compared with the single strain form in other articles,the electrical properties of LDMOS under six forms of mechanical strain were comprehensively studied.Briefly,NLDMOS could increase the current by 5.3%,4.3%and10.4%,respectively,under parallel,perpendicular and biaxial tensile strain of 160MPa.Under the strain of-160MPa parallel compressive strain and 160MPa perpendicular tensile strain,PLDMOS can increase the current by 4%and5.8%,respectively,while the effect of biaxial strain on PLDMOS is very small.It is well proven that mechanical strain can increase the drain current(I_d)without reducing the LDMOS breakdown voltage(V_BD).Meanwhile,the trade-off relationship between on-resistance and breakdown voltage can be improved significantly.Furthermore,the effect of strain was found to be closely related to the size of the device.The longer the gate length is,the more significant the effect of strain is.The piezoresistive coefficients of NLDMOS and PLDMOS under parallel strain were also extracted which were-31.4×10^-11pa^-1 and 55.2×10^-11pa^-1,respectively.Last but not least,the effect of six types of the static and turn-off characteristics to SOI-LIGBT under mechanical strain was analyzed.It was found that SOI-LIGBT can increase the collector current(I_C)greatly under the effect of 200MPa parallel and biaxial tensile strain without changing the breakdown and threshold voltage.It was also illustrated that there would be a peak current of up to 22%and 20%in the linear region.The perpendicular tensile strain of 200MPa increased slowly and gradually saturated after the current change reached 4%.Parallel and biaxial tensile strain were found to increase the carrier density and mobility significantly.The increase in electron mobility would consequently reduce the on-voltage drop(V_on)while the increase in hole density would increase the turn-off time(t_off)and turn-off loss(E_off).Due to the slight decrease in hole density and the increase in electron and hole mobility,V_on,t_off and E_off could reduce simultaneously under perpendicular tensile strain,trade-off relationship between the turn-on voltage drop and turn-off loss could be improved.