Research On Low Rank Tensor Approximate Yield Algorithm For High-dimensional SRAM Column Circuits

As integrated circuit manufacturing processes enter the nanoscale,the impact of process variation on circuit performance is becoming more and more complex.At the same time,integrated circuits are developing towards higher integration and larger circuit scale.There are more parameters affected by process variation,and exhibits obvious high-dimensional characteristics.A yield analysis algorithm suitable for high-dimensional circuits is urgently needed to be proposed.This thesis proposes a novel fast yield analysis algorithm for 4? yield requirements and high-dimensional SRAM column circuits based on Low Rank Tensor Approximation(LRTA)model.The core idea of the algorithm is to use the LRTA model to establish the mapping relationship between input process parameters and output performance,LRTA model can be used to replace time-consuming transistor-level simulations.The polynomial degree of the LRTA model only increases linearly with the dimension,which makes it very suitable for highdimensional circuit problems.In addition,a sensitivity analysis method based on the LRTA model is proposed to obtain the importance of the parameters.By eliminating the unimportant parameters,the yield analysis speed is further improved.The performance of LRTA is validated by SRAM cells and SRAM array circuits.For 18-dimensional SRAM cell,the LRTA method is 5727 times faster than the MC method,and 3-8times faster than other algorithms.For 597-dimensional SRAM array circuits,the HSCS and AIS method methods cannot converge to the correct value in this scenario,the LRTA method is2234 times faster than the MC method and 4.8 times faster than the MFRIS method.The experiment also shows that the sensitivity analysis method based on the LRTA model is highly consistent with the results of the MC method.The model reduction by sensitivity analysis can effectively accelerate the yield estimation process and provide acceptable accuracy.