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Research On 3D NoC Test Planning Based On Pipeline Calculation

Posted on:2022-04-14Degree:MasterType:Thesis
Country:ChinaCandidate:Y BaiFull Text:PDF
GTID:2518306554472574Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
With the continuous development of integrated circuit technology,the integration and complexity of chips continue to increase,Network-on-Chip(No C)is gradually developing towards the direction of three-dimensional architecture.The three-Dimensional Network-on-Chip(3D No C)is formed by stacking 2D No C in the vertical dirrction by the Through Silicon Vias(TSV)technology to realize the interconnection between layers,which reduces the length of the interconnection line and improves the integration of the whole system.However,as the number of integrated IP cores on 3D No C gradually increases,the interconnection between IP cores becomes more complex,which increases the difficulty of testing 3D No C IP cores.Therefore,an efficient 3D No C test planning scheme is proposed under various constraints to reduce test time and chip test costs,which has important research value.In order to solve the problem of the difficulty of test scheduling and low parallel test efficiency of 3D No C IP cores,this paper proposes a 3D No C test planning method based on pipelining calculation in combination with the testing characteristics of 3D No C.Firstly,the structural characteristics of 3D No C and the related technologies of IP core testing are analyzed,and the reuse of No C is used as the testing access mechanism;Then,under the dual constraints of total power consumption and layer power consumption,the multicast pipeline parallel testing method is adopted to test the on-chip isomorphism cores,and a test strategy combining with improved XYZ routing algorithm is proposed to test the heterogeneous cores;Finally,based on the above test strategy,an improved artificial bee colony algorithm is proposed and the corresponding coding method is designed,and the test planning problem is mapped to the improved ABC algorithm optimization problem,so as to find the best test planning scheme.The typical circuits of ITC'02 test benchmarks were used as the experimental objects,the simulation results show that the proposed test method is superior to other test scheduling optimization methods,which can effectively improve test efficiency and reduce test cost;The improved XYZ routing algorithm can alleviate the degree of network congestion,avoid the long waiting time caused by resource conflict,and realize the secondary optimization of the total test time of the system;The improved ABC algorithm can efficiently and quickly find the best test planning scheme and shorten the test time.Compared with other methods,the optimization rate of the maximum test time of the proposed method can reach 15.76%,which effectively improves the test efficiency.
Keywords/Search Tags:Three-Dimensional Network-on-Chip, Test sheduling, Pipelining calculation, XYZ routing algorithm, Improved artificial bee colony algorithm
PDF Full Text Request
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