Study Of Memristor-based Convolutional Neural Networks Architecture

Convolutional neural networks(CNNs)is one of the important implementation methods of deep learning algorithm,and has broad application prospects in the fields of image recognition and video processing.However,as the demand continues to expand,CNNs lead to an exploding number of network synapses and neurons in which the relevant hardware and computation costs will be huge.Memristors have the advantages of low power consumption,small size,and fast reading and writing speed,and can quickly realize the multiply-accumulate computation,which has significant advantages in hardware implementation of CNNs.Therefore,this thesis focuses on the memristor-based convolutional neural networks architecture.The main work of the thesis is as follows:In Chapter 2,we focus on optimizing the accuracy of memristor-based CNNs.We study the architecture of monolithic array CNNs.The main research contents include the network structure of the monolithic array CNNs,the array mapping method,the optimization of the activation function and the performance metrics function(PMF).The basic structure of the network and the mapping method are mainly introduced in Section2.1.In Section 2.2,the performance of the absolute value activation function in the network and the PMF designed for the characteristics of the network structure are analyzed.Finally,the simulation performance of the network under ideal conditions and non-ideal conditions is introduced in Section 2.3.In Chapter 3,the CNNs architecture based on multi-chip array interconnects for the problem of limited support capacity of monolithic arrays is studied.An interconnect CNNs architecture of“M-N-P”mode is proposed.Section 3.1 introduces the basic architecture of the multi-chip interconnected CNNs,including the basic computational units and interconnection methods that make up the interconnect CNNs architecture.Next,the array implementation of the network is introduced in Section 3.2,including the array implementation of the basic computational unit,the mapping method of the general algorithm,and the mapping method of the network in multi-chip arrays.Finally,in Section3.3,the simulation experiments of multi-chip interconnected CNNs are carried out under ideal conditions and non-ideal conditions.In Chapter 4,aiming at the difficulty in the preparation of multi-level devices,an algorithm based on the construction of CNNs with few levels is proposed.This chapter first introduces the idea of the algorithm in detail in Section 4.1,and introduces the design and algorithm implementation of the algorithm.Then,Section 4.2 demonstrates the simulation performance of monolithic CNNs and interconnected CNNs architectures with the algorithm under ideal and non-ideal conditions.In Chapter 5,aiming at the problem that the non-ideality of the array seriously affects the performance of the neural network,a neural network calibration algorithm based on input splits is proposed.This chapter first introduces the design and implementation of the algorithm in Section 5.1.It also describes how to calibrate in a perceptron and CNNs.A simulation experiment was carried out in Section 5.2 to demonstrate the performance of the calibration algorithm in the neural network.The content studied in this thesis can provide a new idea for the realization and application of memristor-based convolutional neural networks,which is expected to promote the further development of memristor-based neuromorphic computing.