Design Of Adaptive Weight LDPC Decoder

In a partially parallel or fully parallel LDPC decoder architecture,as the dimension of the sparse check matrix increases,calculating and storing the second minimum value has become a key factor restricting the throughput and area of the decoder.In view of the above research background and problems,this article mainly does the following work:1.This thesis proposes an adaptive weight MS algorithm(awMS).This algorithm does not need to calculate the second minimum value,but is calculated by the first minimum value.In this thesis,a linear equation related to the input of the check node and an adaptive coefficient that changes with the number of iterations are introduced to calculate the second minimum value to improve the error correction performance and speed up the convergence speed.Compared with the single-minimum MS algorithm(smMS),the proposed awMS algorithm has a performance improvement of about 0.2db under the condition of a signal-to-noise ratio of 4db-4.4db.Compared with the variable weight MS algorithm(vw MS),the error correction performance is improved.The error correction performance of the awMS algorithm is equivalent to that of the NMS algorithm.2.In order to solve the problem of the excessive number of bits passed from the check node to the variable node of the awMS decoding algorithm,which leads to increased hardware resource consumption,this thesis proposes a simplified adaptive weight MS algorithm(sawMS).The proposed algorithm optimizes the calculation process and compresses the calculated results.The sawMS decoding algorithm has no loss in error correction performance and can converge faster.3.Combining sawMS decoding algorithm,this thesis uses hardware construction language(HCL)Chisel to realize a parallel LDPC decoder with pipeline and register group.The design of the pipeline can increase the system clock frequency and data throughput rate,and the register group stores the calculated intermediate value and check node information value.This thesis uses 55nm CMOS process to realize RS-LDPC decoder.The decoder performs up to 8 iterative decoding of data,with a core area of 1.7mm~2 and a throughput rate of 29Gbps under the conditions of a signal-to-noise ratio of 4.4db.The decoding speed of the LDPC decoder meets the requirements of the IEEE 802.3an standard and has certain advantages compared with other decoders of the same type in terms of area and throughput.