Design And Verification Of A Fibre Channel Transceiver

Fibre Channel technology is a high-speed network storage and switching technology that provides long-distance and high-bandwidth data transmission.It is primarily used to connect computer storage devices and enables the transfer of large data files between servers,storage,and client nodes.Fibre Channel is standardized by the T11 Technical Committee of the International Committee for Information Technology Standards,and the technology has been widely used in avionics,storage area networks,and other fields.Autonomous design and verification of Fibre Channel transceivers will contribute to the development and improvement of FC technology in China.With the advancement of nanoscale process technology,system architects are able to accomplish more functions in a single-chip design,making on-chip verification increasingly complex as well.Efficient on-chip verification has become exceptionally important,and the main verification is now performed using the UVM verification methodology.This thesis starts with a brief overview of the important elements of the Fibre Channel protocol such as functional hierarchy,topology and class of service.It also gives a brief introduction to the main verification methodologies at this stage,including verification platforms and verification flow.The UVM verification methodology is mainly introduced,including the basic components that constitute the UVM verification platform,the TLM communication in UVM,several important mechanisms in UVM and the most important sequence mechanism that generates incentives.This thesis then describes in detail how to design a Fibre Channel transceiver,the function to be achieved is to collect information from the optical module,store it in the cache after conversion,or send the data in the cache to the optical module after conversion,that is,to achieve the work of sending and receiving information.The design of FC-0layer includes Xilinx IP high-speed serial transceiver GTX,the cache of data and information is mainly used Xilinx IP-asynchronous The data and information cache is mainly implemented using Xilinx IP-asynchronous FIFO,and the other modules are designed on their own.Constraining the input clock to 125 Mhz with an establishment time margin of 9.746 ns and a hold time margin of 0.058 ns enables the GTX transmission rate to reach a speed of 2.125 Gbps.Then this thesis builds a UVM verification platform for the designed Fibre Channel transceiver,containing the main verification components interface,item,driver,monitor,sequencer,agent,reference model,scoreboard,environment,test and sequence,etc.The verification is done by dividing the Fibre Channel transceiver into transmit clock domain and receive clock domain according to the clock domain,and then building the UVM verification platform separately.Finally,in this thesis,sequence is written on the built verification platform to complete frame format test,original language signal test,original language sequence test and abnormal input test at RX side,and original language protocol test,group frame test and credit recovery test at TX side,respectively.Finally,the code coverage and functional coverage are collected,and also combined with the terminal output information,the correctness of the Fibre Channel transceiver function is obtained after analysis and the verification is completed.