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Design And Implementation Of General Data Generating Module Hardware Circuit

Posted on:2022-07-05Degree:MasterType:Thesis
Country:ChinaCandidate:Z N HuangFull Text:PDF
GTID:2518306524979309Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
Data generators are widely used in electronic information industry because of outputing complex digital excitation signals.With the diversification of data interface types,the general data generation module with the ability to be compatible with different data interface types has become the focus of research.By analyzing the data interface type,data transmission rate and data width of different DACs,this thesis designs a generic data generation module compatible with CMOS,LVDS and JESD204 B interface DACs.The specific work content is:1.Overall scheme design.Through the analysis of the data rate and pin number of the CMOS,LVDS and JESD204 B interfaces of different DACs,FPGA is selected as the controller of the generic data generation module,and the FMC interface is used as the interface of the generic data generation module;compare the data transmission rate of PCI bus and PCIe bus,Use PCIe with a higher transmission rate for bus design;analyze and compare the read rate and storage capacity of SRAM and SDRAM,and use DDR3 SDRAM with large storage capacity and fast access speed as data storage.2.Hardware circuit design.Analyze the pin requirements of PCIe bus interface,DDR3 SDRAM data memory and FMC interface,compare and select FPGA;By analyzing the connection mode of FPGA and DDR3 SDRAM data memory,the data generation module is designed.According to the design indicators,pin allocation between FMC interface and FPGA is carried out to achieve the compatibility of CMOS,LVDS and JESD204 B interface..3.FPGA logic design.Use PCIe hard core to design the bus of general data generation module and realize data communication with the host computer.Use AXI bus to connect PCIe DMA and DD3 SDRAM read-write control IP core,carry out data transfer between bus interface and data memory and complete data storage.The AXI DMA IP core is used to design the data reading logic and realize the data reading.Through the discussion of CMOS,LVDS and JESD204 B interface data transmission methods,complete the data transmission logic design of different data interfaces and realize data output.After testing and verification,the general data generation module has a storage capacity of 8GB,is compatible with CMOS,LVDS,and JESD204 B interfaces,and the maximum pin output rate is 300 Mbps,1250Mbps,and 6.25 Gbps.
Keywords/Search Tags:Generic data generation module, Multi-interface compatibility, Deep storage, FMC interface
PDF Full Text Request
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