Readout Circuit Design Of Single-photon Detector For Space Laser Communication

Space laser communication is a new communication technology with laser as the information carrier.Compared with traditional radio frequency(RF)communication,laser communication does not need a band license and has better performance in deep-space ultra-long distance transmission.With faster communication speed,preferable anti-interference,and superior confidentiality,smaller and lighter terminal equipment,it is expected to be the next generation of deep space communication technology which is hoped to replace RF communication and has attracted plenty of attention in the aerospace application.Due to its single-photon detection capability and easy integration,the free-running Geiger mode avalanche photodiode(Gm-APD)detector array is one of the ideal choices for receiving signals at the end of deep-space laser communication spacecraft.However,the readout integrated circuit(ROIC)of the Gm-APD array for communication faces several difficulties.Firstly,the design of data readout timing and circuit architecture is complex owning to the asynchronous operation between pixels in free-running mode.Secondly,the design of high-speed data output is facing great challenges due to the huge output data of array and the high frame rate readout requirement in communication application.This paper presents the study and design of the ROIC architecture and high-speed output of the Gm-APD array for space laser communication.A 32×32 variable-period asynchronous ROIC chip for laser communication is designed,and the following research work is carried out to solve the problem of high-speed output:the high-speed response model and optimization method of the driving circuit are studied to improve the output bandwidth of the area array bus;a variable period scanning circuit is proposed to realize efficient readout by compressing invalid data.The main research contents and achievements are as follows:(1)Aiming at the problem of high-speed data output,the high-speed data drive circuit model is studied to improve the data transmission ability of the bus in the array.Through lumped model and transfer function analysis,the key parameters affecting output bandwidth are qualitatively identified.Furthermore,based on the Elmore delay model and RC?(N-1)bus distributed parameter model,an accurate expression of response time constant is established.On this basis,the relationship between each design parameter and bandwidth and power consumption is simulated and analyzed,and the optimal design of output stage size which can maximize bandwidth is obtained.The results show that the optimal design size of the output stage and bus can effectively improve the output bandwidth.Under the typical 0.18?m CMOS process and specific power consumption and area limitation conditions,the 3d B bandwidth of the two driving circuits can reach 293 MHz and 395 MHz respectively.(2)This paper innovatively designs a variable-period fast-scanning circuit that can compress invalid-data.The scanning circuit can generate a gating signal with specified width through phase difference operation.The circuit can be integrated into the pixel thanks to the simple structure and the 320?m~2 small layout area.The simulation results show that the circuit can generate a single-cycle/multi-cycle(1T/n T)gating signal adaptively according to the fired situation of pixels,effectively compress the output data of non-fired pixels,and greatly improve the efficiency of array data scanning and output in sparse photon detection scene.(3)A 32×32 asynchronous ROIC for the Gm-APD array is designed based on the0.18?m 6M1P standard CMOS technology.The chip area is about 40 mm~2 and the center to center spacing of the pixels is 100?m.The whole architecture and timing design of asynchronous ROIC is completed.On this basis,the whole process design of the specific circuit modules in the readout architecture is carried out.The test results show that the chip meets the basic functional requirements,which can distinguish the arrival time of photons and achieve high-efficiency data output according to the fired situation of the array.Under the condition of laboratory ambient light,the overall power consumption of the chip is about 195 mW with 15.6 V bias and 20 MHz clock input.