Research On Radiation Hardened Design Methodology Of ASIC Based On Triple Modular Redundancy

With the development of the times,the aerospace field has become the important symbol of a country's comprehensive national strength.Its development has brought various conveniences to people's lives and provided an important guarantee for national defense.The radiation environment in space is extremely harsh,and the high-energy particles in it will cause radiation effects such as single event effects and total dose effects on Application Specific Integrated Circuit(ASIC)chips widely used in spacecraft.Single event upset(SEU)is the most common radiation effect.And with the development of integrated circuit technology,in the daily environment,ASIC may also be interfered by electromagnetic radiation,causing its function to malfunction.All of these make the research of the radiation hardened technology of ASIC become an important research content.In order to improve the radiation hardened performance of ASIC chips,researchers have carried out a lot of research work and put forward many technical means to realize the radiation hardened design of the chip,such as Triple Modular Redundancy(TMR).TMR is a common and effective means to improve the resistance to SEU.Based on the principle of TMR and its derivative structure,this paper proposed a new enhanced Space-Time TMR(EST?TMR)structure: TMR?5DFF.The proposed TMR?5DFF structure replaces the two-stage latches that make up EST?TMR with flip-flops.TMR?5DFF realizes the edge trigger and solves the problem that the two-stage latches that make up EST?TMR are simultaneously turned on.At the same time,this paper further improved the TMR?5DFF structure,and proposed Mixed TMR?DFF(MTMR?DFF),which effectively reduced the circuit area and power consumption.After that,this paper separately researched on the radiation hardened design methodology based on the Second Synthesis of Modified Netlist(SSMN)and the radiation hardened design methodology based on the Establishment of Standard Cell Library(ESCL).Based on the0.35?m process of TSMC and the proposed MTMR?DFF structure,this paper realized the radiation hardened design of the Universal Asynchronous Receiver/Transmitter(UART)circuit to verify the two radiation hardened design methodologies.At the same time,this paper researched on the Design for Testability(DFT)of the radiation hardened circuits,and implemented DFT for the radiation hardened UART circuit,inserted the scan chain,realized the full scan design,and carried out Automatic Test Pattern Generation(ATPG).The test coverage rate reached more than 97%.Finally,this paper used the method of fault injection to verify the anti-irradiation function of the radiation hardened UART circuits which adopted the method of SSMN and the method of ESCL respectively to achieve radiation hardened design.Moreover,through the summary of the performance of the radiation hardened UART circuits and the unreinforced UART circuit,this paper compared and analyzed the different radiation hardened design methodologies of ASIC,and looks forward to the future work.