Integrated Circuit Design For High Precision Electrical Impedance Tomography System

Electrical impedance tomography(EIT)is a new imaging technology with many potential medical,and it complements the current medical imaging methods.Compared with traditional imaging technologies,such as Computed Tomography(CT)and Magnetic Resonance Imaging(MRI),EIT does not comes with any radiation effect.Hence,we can be subjected to EIT multiple times without being exposed to harmful radiation.Currently,EIT systems based on discrete components are commercially available,but these systems are large in size,complicated to use and large in power consumption.Hence,it is important for us to develop a small in size,low power,portable system using integrated circuit chips.In my dissertation,I have designed our next generation of EIT chip based on the digital lock-in amplifier with switched ratio-metric technology architecture.The key building blocks of our EIT system consists of two parts:reconfigurable excitation current source and voltage read-out module.The requirement for our reconfigurable excitation current source is to design>500?A_p-p amplitude and>500k Hz excitation frequency.To achieve a Spurious Free Dynamic Range(SFDR)>60d B,the current driver requires an output impedance of at least 1M?.We proposed digital synthesis method to generate the sinusoidal signal and a fully differential current-voltage feedback current driver.This design provides a four-step adjustable configuration of the excitation frequency from 50k Hz,100k Hz,500k Hz to1MHz in the simulation.The maximum excitation current is 800?A_p-p.The output impedance can reach 1.8M?and the total harmonic distortion is less than 0.3%.The voltage read-out module mainly consists of(1)the pre-demodulation circuit,(2)the pre-amplification circuit,and(3)the analog-to-digital converter.The pre-demodulation circuit pre-demodulates the front-end signals from different excitation frequencies to a relatively low frequency(10k Hz),greatly reduce the requirement for the bandwidth of the pre-amplification circuit.The pre-amplification circuit lowers the input referred noise and increases the input impedance while providing a gain of20?58d B.The automatic gain control circuit based on level crossing structure is proposed to realize a read-out range of 100?V?10m V.Our proposed architecture eliminate the need of power hungry peak detector circuit,which helps us to achieve a total power consumption of 0.9?W.In this dissertation,a 12-bit 1.6-MS/s successive approximation register analog-to-digital converter is used for signal sampling.The equivalent number of bits(ENOB)is 11.38bit from our post-layout simulation.In addition,a substrate-switched bootstrap switch is proposed in this dissertation to improve its linearity.The current consumption of the entire front-end read-out circuit is 54?A and a sensitivity of 53m?_rmscan be achieved in the resistance measurement.The EIT chips are implemented based on the X-FAB 0.18?m process.They are separated into two chips:EIT1901 and EIT1902,with chip areas of 3.75mm² and 2.125mm²,respectively.The testing plan for our EIT system is also presented.