Design And Optimization Of High Precision Stochastic Computing Units

Stochastic computing(SC)transfers the traditional binary signal to a probability sequence so that complex binary operations can be implemented by basic logic gate circuits in the probability domain,thus SC can be used to reduce the extremely high calculation complexity of chips in the era of big data.However,the precision of the SC is not satisfactory.To apply it in highly complex very large-scale integration(VLSI)circuits,high-precision SC computational units need to be designed.Since the precision of the SC multiplier is greatly affected by the correlation of the input sequences,this paper first proposes a correlation independent SC multiplier based on rematching,which can obtain the best accuracy when only the distribution of one input sequence is known.Besides,considering the conversion cost of binary numbers and SC sequences,this paper designs a sequence converter based on comparison-and-following,which can convert integer sequences to SC sequences without introducing additional delay.Based on the two proposed basic units,this thesis applies SC to deep neural network(DNN)image classification and massive multiple-input multiple-output(MIMO)detection.Firstly,a high-precision SC-based DNN is designed,and then a length adaptive method that dynamically adjusts the sequence length according to the input is proposed.The SC-based DNN can achieve an accuracy loss of 0.01%with only 20-bit sequence length on the MNIST dataset,thereby solving the problem of long SC length in the current study.In addition,a massive MIMO detection algorithm based on SC is proposed,which adopts deep learning to solve the detection under correlation channels.By proposing the partition scaling method and weight transfer strategy,the entire detection process can be realized in the probability domain.Compared with the floating-point algorithm,the performance loss of the proposed algorithm is only 0.8 d B at the bit error rate of 10^-4.Since the core of the above two algorithms is the DNN,so this thesis also implements the ASIC circuit of the SC-based DNN.Layout simulation results on the SMIC 40 nm process library show that this design achieves a throughput up to 25M images/s and area efficiency of 10.3M images/s/mm².Compared with similar work,this design can improve the area efficiency by about 16 times,thus confirming SC can solve the high computational complexity of chips in the era of big data.