Design And Implementation Of Cell Search And Random Access In Massive MIMO Systems

In order to meet the development needs of the future intelligent society,the 5th Generation Mobile Communication Systems(5G)need to have higher spectrum utilization,transmission rate,network capacity,reliability and wireless coverage performance,while greatly reducing the transmission delay,power consumption and cost of the mobile communication system.As one of the core technologies of 5G wireless communication,the massive Multiple Input Multiple Output(MIMO)is widely regarded as an effective method to improve the capacity and reliability of wireless communication systems in the development of future mobile communication systems because of its great potential in deeply digging space resources,improving spectrum efficiency and power efficiency.This dissertation is oriented towards 5G massive MIMO prototype verification system,and carries out research on the massive MIMO physical random access channel and polar codes encoder and decoder in the context of massive MIMO cell search and random access on the system.Meanwhile,the hardware implementation of Field Programmable Gate Array(FPGA)is finished on the platform.First of all,the configuration of wireless frame structure,physical resources,system frequency and bandwidth in 5G systems based on communication protocol standards are reviewed.Based on this,the cell search process in 5G system is researched,including briefly describing the set of synchronous broadcast block set sent by the base station on the downlink and discussing the primary synchronization signal detection,secondary synchronization signal detection and physical broadcast channel detection during the cell search process.Secondly,the random access process in the 5G system is studied,mainly including the preamble sequence sent by the user in the physical uplink random access channel,the detection of physical random access channel by the base station,and the uplink timing advance of the user.Finally,the massive MIMO prototype verification system is outlined.Secondly,the design and implementation of massive MIMO physical random access channel for 5G evolution are completed.Based on the massive MIMO channel model and physical random access channel process,the sparse characteristic of the massive MIMO beam domain channel is utilized to limit the signal processing to a small number of beams,thereby reducing the complexity of the massive MIMO random access channel receiver.Based on this,the design of physical random access channel transmitter is studied in accordance with the 5G communication protocol standard,and the generation process of physical random access channel preamble sequence transmitter is simplified to obtain a low complexity random access channel transmitter structure.Furthermore,the dissertation studies the design of physical random access channel receiver,and obtains a massive MIMO timing estimation method in antenna domain based on the maximum likelihood criteria.At the same time,the method can be analogized to the beam domain processing,and the cross correlation operation is concentrated on a few high energy beam domain signals,thereby greatly reducing the implementation complexity,and the beam domain random access channel receiver implementation structure is given.Further,the logic design of each part module is given according to the proposed low complexity random access channel transmitter and receiver structure.Finally,the dissertation gives the FPGA implementation on the hardware platform,and the resource consumption.Finally,the design and implementation of 5G polar codes encoder and decoder are completed on the prototype verification system.Firstly,the channel polarization theory of polar codes is reviewed,including the process of channel separation and channel combination.Based on this,the dissertation studies the 5G polar codes encoding algorithm,discussing the encoding method of the polar codes generation matrix and the butterfly operation.Secondly,the 5G polar codes decoding algorithm is studied.It mainly focuses on the algorithm implementation principle,and the decoding performance and throughput of different algorithms at the different code lengths and rates.Further,a pipeline implementation structure of the polar codes encoder is given based on the butterfly algorithm,and an effective polar codes decoder implementation structure is given based on the FSL decoding algorithm.The polar codes decoder adopts a reasonable operation parallelism,code block parallelism,and pipeline structure to ensure that the decoder throughput is improved under the condition of certain resources.Finally,it gives the FPGA implementation on the hardware platform,hardware test and resource consumption.